{"id":"https://openalex.org/W2040553481","doi":"https://doi.org/10.1142/s0218126699000153","title":"A CHARGE RECYCLING TECHNIQUE FOR THE DESIGN OF LOW POWER CMOS CLOCK DRIVERS","display_name":"A CHARGE RECYCLING TECHNIQUE FOR THE DESIGN OF LOW POWER CMOS CLOCK DRIVERS","publication_year":1999,"publication_date":"1999-06-01","ids":{"openalex":"https://openalex.org/W2040553481","doi":"https://doi.org/10.1142/s0218126699000153","mag":"2040553481"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126699000153","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126699000153","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023894427","display_name":"S. Nikolaidis","orcid":"https://orcid.org/0000-0002-9794-8062"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"S. NIKOLAIDIS","raw_affiliation_strings":["Electronics & Computers Division,  Dept. of Physics, Aristotle Univ. of Thessaloniki, 54006  Thessaloniki, Greece","Electronics & Computers Division, Dept. of Physics, Aristotle Univ. of Thessaloniki, 54006 Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics & Computers Division,  Dept. of Physics, Aristotle Univ. of Thessaloniki, 54006  Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]},{"raw_affiliation_string":"Electronics & Computers Division, Dept. of Physics, Aristotle Univ. of Thessaloniki, 54006 Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058522486","display_name":"E.D. Kyriakis-Bitzaros","orcid":"https://orcid.org/0000-0002-4497-6158"},"institutions":[{"id":"https://openalex.org/I203474044","display_name":"National Centre of Scientific Research \"Demokritos\"","ror":"https://ror.org/038jp4m40","country_code":"GR","type":"facility","lineage":["https://openalex.org/I203474044"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","GR"],"is_corresponding":false,"raw_author_name":"E. D. KYRIAKIS-BITZAROS","raw_affiliation_strings":["Institute of Microelectronics, NCSR  \"Demokritos\", 15310 Agia Paraskevi, Greece","Institute of Microelectronics, NCSR \"Demokritos\", 15310 Agia Paraskevi, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, NCSR  \"Demokritos\", 15310 Agia Paraskevi, Greece","institution_ids":["https://openalex.org/I4210119392"]},{"raw_affiliation_string":"Institute of Microelectronics, NCSR \"Demokritos\", 15310 Agia Paraskevi, Greece","institution_ids":["https://openalex.org/I203474044"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13842945,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"09","issue":"03n04","first_page":"169","last_page":"180"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7064692974090576},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6424593925476074},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5732241868972778},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5007228851318359},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4943504333496094},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.49372896552085876},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4796641170978546},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.45554250478744507},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4537714421749115},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4425990879535675},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.43746417760849},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.4245019257068634},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4202510118484497},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.41449400782585144},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3554132580757141},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.27264878153800964},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.20931857824325562},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10421741008758545},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.0855344831943512}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7064692974090576},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6424593925476074},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5732241868972778},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5007228851318359},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4943504333496094},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.49372896552085876},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4796641170978546},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.45554250478744507},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4537714421749115},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4425990879535675},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.43746417760849},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.4245019257068634},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4202510118484497},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.41449400782585144},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3554132580757141},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.27264878153800964},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.20931857824325562},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10421741008758545},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0855344831943512},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126699000153","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126699000153","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8500000238418579,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1967514275","https://openalex.org/W2058326812","https://openalex.org/W2071693325","https://openalex.org/W2122984966","https://openalex.org/W2155755017","https://openalex.org/W2164693079","https://openalex.org/W2170619886","https://openalex.org/W2172290836","https://openalex.org/W2537923031"],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2474747038","https://openalex.org/W3006003651","https://openalex.org/W2052455055","https://openalex.org/W2090237663","https://openalex.org/W2137310043","https://openalex.org/W2107437643","https://openalex.org/W1865286884","https://openalex.org/W2161776375","https://openalex.org/W2096393085"],"abstract_inverted_index":{"The":[0,41],"design":[1,80],"of":[2,27,49,55,69,78,128],"low":[3],"power":[4,93,107],"CMOS":[5],"clock":[6,20,39],"drivers":[7],"using":[8,60],"a":[9,19,126],"charge":[10,29],"recycling":[11],"technique":[12],"is":[13,35,122,132],"introduced":[14],"in":[15,31,37],"this":[16],"paper.":[17],"Considering":[18],"signal":[21],"and":[22,64,75],"its":[23,83],"complement,":[24],"the":[25,28,32,45,50,53,70,76,100,105,129],"half":[26],"stored":[30],"load":[33,102],"capacitances":[34],"reused":[36],"every":[38],"edge.":[40],"proposed":[42],"circuit":[43,71],"exploits":[44],"inherent":[46],"input-output":[47],"delay":[48],"driver":[51],"for":[52,99],"generation":[54],"all":[56],"necessary":[57],"control":[58,116],"signals,":[59],"fully":[61],"digital":[62],"logic":[63],"conventional":[65],"technology.":[66],"Extensive":[67],"simulations":[68],"have":[72],"been":[73,86],"performed":[74],"influence":[77],"various":[79],"parameters":[81],"on":[82],"response":[84],"has":[85],"studied.":[87],"Compared":[88],"to":[89,112,115],"traditional":[90],"taper":[91],"buffers,":[92],"savings":[94],"over":[95],"45%":[96],"are":[97],"obtained":[98],"output":[101],"transitions":[103],"whereas":[104],"total":[106],"reduction":[108],"decreases":[109],"by":[110],"10%":[111],"35%":[113],"due":[114],"overhead.":[117],"Moreover,":[118],"no":[119],"speed":[120],"degradation":[121],"observed":[123],"but":[124],"almost":[125],"duplication":[127],"silicon":[130],"area":[131],"required.":[133]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}