{"id":"https://openalex.org/W2034326903","doi":"https://doi.org/10.1142/s0218126691000057","title":"ANALOG MOS VECTOR MULTIPLIERS FOR THE IMPLEMENTATION OF SYNAPSES IN ARTIFICIAL NEURAL NETWORKS","display_name":"ANALOG MOS VECTOR MULTIPLIERS FOR THE IMPLEMENTATION OF SYNAPSES IN ARTIFICIAL NEURAL NETWORKS","publication_year":1991,"publication_date":"1991-06-01","ids":{"openalex":"https://openalex.org/W2034326903","doi":"https://doi.org/10.1142/s0218126691000057","mag":"2034326903"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126691000057","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126691000057","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5105414818","display_name":"Fathi M. A. Salam","orcid":null},"institutions":[{"id":"https://openalex.org/I87216513","display_name":"Michigan State University","ror":"https://ror.org/05hs6h993","country_code":"US","type":"education","lineage":["https://openalex.org/I87216513"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"FATHI M.A. SALAM","raw_affiliation_strings":["Systems and Circuits and Artificial Neural Nets Laboratories, Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Systems and Circuits and Artificial Neural Nets Laboratories, Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824, USA","institution_ids":["https://openalex.org/I87216513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036547069","display_name":"Myung\u2010Ryul Choi","orcid":"https://orcid.org/0000-0003-4311-6241"},"institutions":[{"id":"https://openalex.org/I87216513","display_name":"Michigan State University","ror":"https://ror.org/05hs6h993","country_code":"US","type":"education","lineage":["https://openalex.org/I87216513"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"MYUNG-RYUL CHOI","raw_affiliation_strings":["Systems and Circuits and Artificial Neural Nets Laboratories, Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Systems and Circuits and Artificial Neural Nets Laboratories, Department of Electrical Engineering, Michigan State University, East Lansing, MI 48824, USA","institution_ids":["https://openalex.org/I87216513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I87216513"],"apc_list":null,"apc_paid":null,"fwci":0.9443,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.73982292,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"01","issue":"02","first_page":"205","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9896000027656555,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.7038615942001343},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.6210173964500427},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5792493224143982},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.5788301825523376},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5678107142448425},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5642616748809814},{"id":"https://openalex.org/keywords/analog-signal-processing","display_name":"Analog signal processing","score":0.533798336982727},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5326682329177856},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48236149549484253},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.4473256766796112},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4285619854927063},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.41367006301879883},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.38805466890335083},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.385816365480423},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.26876652240753174},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.25043684244155884},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21100738644599915},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19663646817207336},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18852898478507996},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17512962222099304}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7038615942001343},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.6210173964500427},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5792493224143982},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.5788301825523376},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5678107142448425},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5642616748809814},{"id":"https://openalex.org/C379707","wikidata":"https://www.wikidata.org/wiki/Q2328303","display_name":"Analog signal processing","level":4,"score":0.533798336982727},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5326682329177856},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48236149549484253},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.4473256766796112},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4285619854927063},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.41367006301879883},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.38805466890335083},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.385816365480423},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.26876652240753174},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.25043684244155884},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21100738644599915},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19663646817207336},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18852898478507996},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17512962222099304},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126691000057","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126691000057","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1489445348","https://openalex.org/W2365016061","https://openalex.org/W1624706916","https://openalex.org/W4285819435","https://openalex.org/W1981652693","https://openalex.org/W3047246479","https://openalex.org/W1792053179","https://openalex.org/W2157889377","https://openalex.org/W2103066250","https://openalex.org/W2136192029"],"abstract_inverted_index":{"All-MOS":[0],"analog":[1,16,19,92,104],"vector-vector":[2],"multipliers":[3,66],"are":[4,42],"described":[5],"and":[6,18,87,111],"designed":[7,97],"for":[8],"the":[9,12,47,62,69,107],"implementation":[10],"of":[11,64],"linear":[13],"multiplication":[14],"between":[15],"signals":[17],"synaptic":[20],"weights":[21],"in":[22,58],"artificial":[23,31],"neural":[24,32],"networks":[25,33],"(ANNs).":[26],"Employing":[27],"these":[28,65],"multipliers,":[29],"large-scale":[30],"can":[34],"be":[35],"implemented":[36],"using":[37,106,115],"fewer":[38],"MOS":[39],"transistors":[40],"than":[41],"required":[43],"by":[44,67],"implementations":[45],"employing":[46],"so-called":[48],"Gilbert":[49],"multiplier.":[50],"PSPICE":[51],"circuit":[52],"simulations":[53],"have":[54],"been":[55,96,113],"extensively":[56],"executed":[57],"order":[59],"to":[60],"quantify":[61],"performance":[63],"measuring":[68],"following":[70],"specifications:":[71],"maximum":[72],"percentage":[73],"error,":[74],"output":[75],"offset,":[76],"X":[77,81],"or":[78,82],"Y":[79,83],"nonlinearity,":[80],"feedthrough,":[84],"small-signal":[85],"bandwidth,":[86],"slew":[88],"rate.":[89],"An":[90],"11-dimensional":[91],"vector":[93],"multiplier":[94],"has":[95,112],"on":[98],"a":[99],"40-pin":[100],"MOSIS":[101],"TINYCHIP":[102],"with":[103],"pads":[105],"MAGIC":[108],"VLSI":[109],"tools":[110],"fabricated":[114],"2":[116],"\u03bcm":[117],"CMOS":[118],"n-well":[119],"process":[120],"via":[121],"MOSIS.":[122]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}