{"id":"https://openalex.org/W4386223092","doi":"https://doi.org/10.1142/s0218126624500853","title":"CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits","display_name":"CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits","publication_year":2023,"publication_date":"2023-08-28","ids":{"openalex":"https://openalex.org/W4386223092","doi":"https://doi.org/10.1142/s0218126624500853"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126624500853","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126624500853","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018771469","display_name":"Tabassum Khurshid","orcid":"https://orcid.org/0009-0005-3087-546X"},"institutions":[{"id":"https://openalex.org/I59179055","display_name":"Shri Mata Vaishno Devi University","ror":"https://ror.org/036x6w630","country_code":"IN","type":"education","lineage":["https://openalex.org/I59179055"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tabassum Khurshid","raw_affiliation_strings":["School of Electronics & Communication Engineering, SMVD University, Katra 182320, Jammu and Kashmir, India"],"raw_orcid":"https://orcid.org/0009-0005-3087-546X","affiliations":[{"raw_affiliation_string":"School of Electronics & Communication Engineering, SMVD University, Katra 182320, Jammu and Kashmir, India","institution_ids":["https://openalex.org/I59179055"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024254741","display_name":"Vikram Singh","orcid":"https://orcid.org/0000-0002-8080-0491"},"institutions":[{"id":"https://openalex.org/I59179055","display_name":"Shri Mata Vaishno Devi University","ror":"https://ror.org/036x6w630","country_code":"IN","type":"education","lineage":["https://openalex.org/I59179055"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Vikram Singh","raw_affiliation_strings":["School of Electronics & Communication Engineering, SMVD University, Katra 182320, Jammu and Kashmir, India"],"raw_orcid":"https://orcid.org/0000-0002-8080-0491","affiliations":[{"raw_affiliation_string":"School of Electronics & Communication Engineering, SMVD University, Katra 182320, Jammu and Kashmir, India","institution_ids":["https://openalex.org/I59179055"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024254741"],"corresponding_institution_ids":["https://openalex.org/I59179055"],"apc_list":null,"apc_paid":null,"fwci":0.6322,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.67945159,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":"33","issue":"05","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/carbon-nanotube-field-effect-transistor","display_name":"Carbon nanotube field-effect transistor","score":0.8086634874343872},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6065007448196411},{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.5838916897773743},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5808975100517273},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5598781108856201},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5381705164909363},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5361921787261963},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5241211652755737},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.5002012252807617},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.47721511125564575},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4763372540473938},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4727303087711334},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4693008065223694},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.42730477452278137},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.40445002913475037},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31944000720977783},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.31175827980041504},{"id":"https://openalex.org/keywords/field-effect-transistor","display_name":"Field-effect transistor","score":0.2477191686630249},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.2475104033946991},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23051893711090088}],"concepts":[{"id":"https://openalex.org/C58916441","wikidata":"https://www.wikidata.org/wiki/Q1778563","display_name":"Carbon nanotube field-effect transistor","level":5,"score":0.8086634874343872},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6065007448196411},{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.5838916897773743},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5808975100517273},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5598781108856201},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5381705164909363},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5361921787261963},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5241211652755737},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.5002012252807617},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.47721511125564575},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4763372540473938},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4727303087711334},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4693008065223694},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.42730477452278137},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.40445002913475037},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31944000720977783},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.31175827980041504},{"id":"https://openalex.org/C145598152","wikidata":"https://www.wikidata.org/wiki/Q176097","display_name":"Field-effect transistor","level":4,"score":0.2477191686630249},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2475104033946991},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23051893711090088},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126624500853","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126624500853","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8199999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W2003424444","https://openalex.org/W2004823737","https://openalex.org/W2016710629","https://openalex.org/W2018735115","https://openalex.org/W2025422414","https://openalex.org/W2068871056","https://openalex.org/W2115614135","https://openalex.org/W2121484865","https://openalex.org/W2129502787","https://openalex.org/W2165303371","https://openalex.org/W2169245181","https://openalex.org/W2172161464","https://openalex.org/W2339074292","https://openalex.org/W2592371101","https://openalex.org/W2608484128","https://openalex.org/W2610082426","https://openalex.org/W2807358726","https://openalex.org/W2958071401","https://openalex.org/W2994485499","https://openalex.org/W2996060583","https://openalex.org/W3000249105","https://openalex.org/W3014528999","https://openalex.org/W3028713688","https://openalex.org/W3095588560","https://openalex.org/W3154312436","https://openalex.org/W3174487693","https://openalex.org/W3210186532","https://openalex.org/W4205892671","https://openalex.org/W4206222163","https://openalex.org/W4283381856","https://openalex.org/W4308072542","https://openalex.org/W4323664714"],"related_works":["https://openalex.org/W2491954149","https://openalex.org/W2566374974","https://openalex.org/W4310804573","https://openalex.org/W3210323816","https://openalex.org/W2003024738","https://openalex.org/W3094281021","https://openalex.org/W4386223092","https://openalex.org/W2965775876","https://openalex.org/W4213237977","https://openalex.org/W4379468678"],"abstract_inverted_index":{"The":[0,67,92,165],"advent":[1],"of":[2,69,94,123,125,148],"multi-valued":[3],"logic":[4,19,42,65,119,151],"(MVL)":[5],"systems":[6],"provides":[7],"considerable":[8],"improvements":[9],"in":[10,76,104,121,158,182,195],"energy":[11],"consumption":[12,145],"and":[13,26,50,53,130,146,156,163,174],"computational":[14],"efficiency":[15],"compared":[16,189],"to":[17,143,190],"binary":[18],"systems.":[20],"Using":[21],"resistive":[22],"random-access":[23],"memory":[24],"(RRAM)":[25],"carbon":[27],"nanotube":[28],"field":[29],"effect":[30],"transistors":[31],"(CNTFETs),":[32],"this":[33],"manuscript":[34],"presents":[35],"a":[36,136],"new":[37],"design":[38],"method":[39],"for":[40,102],"ternary":[41,45,48,51,64,118,170,175],"gates":[43,152],"(standard":[44],"inverter":[46],"(STI),":[47],"NOR,":[49],"NAND)":[52],"some":[54],"arithmetic":[55],"circuit":[56,99],"applications":[57],"are":[58,73],"implemented":[59],"based":[60,117],"on":[61],"the":[62,70,88,95,111,149,191,196],"proposed":[63,71,112],"gates.":[66],"simulations":[68],"circuits":[72,120,178],"carried":[74],"out":[75],"Synopsis":[77],"HSPICE":[78],"software":[79],"by":[80],"employing":[81],"32-nm":[82],"Stanford":[83,89],"CNTFET":[84,116],"technology":[85],"along":[86],"with":[87,141,153,184],"RRAM":[90],"model.":[91],"robustness":[93],"designed":[96],"CNTFET-RRAM":[97],"STI":[98],"is":[100,139],"investigated":[101],"variations":[103,157],"process":[105,154],"parameters.":[106],"Simulation":[107],"results":[108],"verify":[109],"that":[110],"designs":[113,194],"outperform":[114],"other":[115,192],"terms":[122],"number":[124],"components,":[126],"power":[127,131,144],"consumption,":[128],"delay":[129,132],"product":[133],"(PDP).":[134],"Furthermore,":[135],"reduced":[137],"change":[138],"perceived":[140],"respect":[142],"PDP":[147,183],"presented":[150,166],"deviation,":[155],"supply":[159],"voltage,":[160],"temperature,":[161],"capacitance":[162],"frequency.":[164],"STI,":[167],"TNAND,":[168],"TNOR,":[169],"half":[171],"adder":[172],"(THA)":[173],"multiplier":[176],"(TMUL)":[177],"exhibit":[179],"an":[180],"improvement":[181],"less":[185],"transistor":[186],"count":[187],"as":[188],"existing":[193],"literature.":[197]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3}],"updated_date":"2026-05-07T13:39:58.223016","created_date":"2025-10-10T00:00:00"}