{"id":"https://openalex.org/W4381167868","doi":"https://doi.org/10.1142/s0218126624500245","title":"Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation","display_name":"Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation","publication_year":2023,"publication_date":"2023-06-19","ids":{"openalex":"https://openalex.org/W4381167868","doi":"https://doi.org/10.1142/s0218126624500245"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126624500245","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126624500245","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092970403","display_name":"Vikas Shivakumar","orcid":null},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]},{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vikas Shivakumar","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, 500078, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, 500078, India","institution_ids":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014347182","display_name":"Chetan Vudadha","orcid":"https://orcid.org/0000-0002-0277-2931"},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]},{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Chetan Vudadha","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, 500078, India"],"raw_orcid":"https://orcid.org/0000-0002-0277-2931","affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, 500078, India","institution_ids":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5014347182"],"corresponding_institution_ids":["https://openalex.org/I4210101034","https://openalex.org/I74796645"],"apc_list":null,"apc_paid":null,"fwci":0.1439,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4591689,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"33","issue":"02","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9682999849319458,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.8100883960723877},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.7952591776847839},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7770995497703552},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7332101464271545},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.5730209946632385},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5370399355888367},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.5351850390434265},{"id":"https://openalex.org/keywords/single-precision-floating-point-format","display_name":"Single-precision floating-point format","score":0.5173213481903076},{"id":"https://openalex.org/keywords/double-precision-floating-point-format","display_name":"Double-precision floating-point format","score":0.4775443971157074},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.4696839153766632},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.4439311623573303},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4389411509037018},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.423290878534317},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3920174539089203},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36184075474739075},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3227831721305847},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20324957370758057},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16098958253860474},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09480509161949158}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.8100883960723877},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.7952591776847839},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7770995497703552},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7332101464271545},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.5730209946632385},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5370399355888367},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.5351850390434265},{"id":"https://openalex.org/C133095886","wikidata":"https://www.wikidata.org/wiki/Q1307173","display_name":"Single-precision floating-point format","level":3,"score":0.5173213481903076},{"id":"https://openalex.org/C35912277","wikidata":"https://www.wikidata.org/wiki/Q1243369","display_name":"Double-precision floating-point format","level":3,"score":0.4775443971157074},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.4696839153766632},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.4439311623573303},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4389411509037018},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.423290878534317},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3920174539089203},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36184075474739075},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3227831721305847},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20324957370758057},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16098958253860474},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09480509161949158},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126624500245","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126624500245","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"id":"https://metadata.un.org/sdg/8","display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1992288365","https://openalex.org/W2061528230","https://openalex.org/W2161395307","https://openalex.org/W2522240413","https://openalex.org/W2623063854","https://openalex.org/W4251674788","https://openalex.org/W4254544948"],"related_works":["https://openalex.org/W3150370983","https://openalex.org/W2239119680","https://openalex.org/W1564887326","https://openalex.org/W3215589575","https://openalex.org/W2116803521","https://openalex.org/W3150959508","https://openalex.org/W1571090276","https://openalex.org/W2773283032","https://openalex.org/W1973800584","https://openalex.org/W2185760795"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,18,48,75,104,127],"realization":[4],"of":[5,21,35,83],"binary":[6,99],"and":[7,40,60,71,85,91,97,113,120],"floating-point":[8,109],"comparators":[9,100],"on":[10,66],"FPGA.":[11],"The":[12,52,78,107],"implementation":[13],"is":[14],"done":[15],"by":[16],"exploiting":[17],"primitive":[19],"instantiation":[20],"FPGA":[22,69],"resources":[23],"which":[24],"has":[25],"enabled":[26],"a":[27],"significant":[28],"improvement":[29,82],"in":[30,33,87,93],"resource":[31],"utilization":[32],"terms":[34],"Look-Up":[36],"Table":[37],"(LUT)":[38],"usage":[39],"overall":[41],"combinational":[42],"path":[43],"delay":[44,94],"when":[45],"compared":[46,73,102,125],"to":[47,103,126],"conventional":[49],"inference":[50],"approach.":[51],"comparator":[53,110],"architectures":[54],"are":[55,72],"implemented":[56],"using":[57],"Vivado":[58],"2020.1":[59],"ISE":[61],"Design":[62],"Suite":[63],"14.7":[64],"environment":[65],"multiple":[67],"Xilinx":[68],"platforms":[70],"with":[74],"existing":[76,105,128],"designs.":[77],"results":[79],"indicate":[80],"an":[81],"33.33%":[84],"45.45%":[86],"LUT":[88],"utilization,":[89],"14.41%":[90],"30.73%":[92],"for":[95,117],"32-bit":[96],"64-bit":[98],"respectively,":[101,124],"architectures.":[106],"proposed":[108],"requires":[111],"88.57%":[112],"285.29%":[114],"lesser":[115],"LUTs":[116],"single":[118],"precision":[119,122],"double":[121],"representation":[123],"design.":[129]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
