{"id":"https://openalex.org/W4307640255","doi":"https://doi.org/10.1142/s0218126623501402","title":"A Novel DDCC-Based Current-Mode Two-Integrator-Loop Active-C Biquad","display_name":"A Novel DDCC-Based Current-Mode Two-Integrator-Loop Active-C Biquad","publication_year":2022,"publication_date":"2022-10-27","ids":{"openalex":"https://openalex.org/W4307640255","doi":"https://doi.org/10.1142/s0218126623501402"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126623501402","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126623501402","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052309419","display_name":"Remzi Arslanalp","orcid":null},"institutions":[{"id":"https://openalex.org/I175124709","display_name":"S\u00fcleyman Demirel \u00dcniversitesi","ror":"https://ror.org/04fjtte88","country_code":"TR","type":"education","lineage":["https://openalex.org/I175124709"]}],"countries":["TR"],"is_corresponding":true,"raw_author_name":"Remzi Arslanalp","raw_affiliation_strings":["Department of Electrical and Electronics Engineering, Suleyman Demirel University, 32260 Isparta, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronics Engineering, Suleyman Demirel University, 32260 Isparta, Turkey","institution_ids":["https://openalex.org/I175124709"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5052309419"],"corresponding_institution_ids":["https://openalex.org/I175124709"],"apc_list":null,"apc_paid":null,"fwci":0.0716,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.31024099,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"32","issue":"08","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-biquad-filter","display_name":"Digital biquad filter","score":0.9099559783935547},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.8082630634307861},{"id":"https://openalex.org/keywords/passive-integrator-circuit","display_name":"Passive integrator circuit","score":0.6382867693901062},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5345807075500488},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.5208030939102173},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.5124804973602295},{"id":"https://openalex.org/keywords/block-diagram","display_name":"Block diagram","score":0.4819662272930145},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47907787561416626},{"id":"https://openalex.org/keywords/active-filter","display_name":"Active filter","score":0.47618570923805237},{"id":"https://openalex.org/keywords/chebyshev-filter","display_name":"Chebyshev filter","score":0.431276798248291},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.42332321405410767},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.4069581925868988},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.39360716938972473},{"id":"https://openalex.org/keywords/low-pass-filter","display_name":"Low-pass filter","score":0.3748881220817566},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2194596529006958},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.190714031457901},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.173036128282547},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1385849416255951},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.13490626215934753},{"id":"https://openalex.org/keywords/rc-circuit","display_name":"RC circuit","score":0.11803832650184631},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10137948393821716},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08720433712005615}],"concepts":[{"id":"https://openalex.org/C14455310","wikidata":"https://www.wikidata.org/wiki/Q5276043","display_name":"Digital biquad filter","level":4,"score":0.9099559783935547},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.8082630634307861},{"id":"https://openalex.org/C30839866","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Passive integrator circuit","level":5,"score":0.6382867693901062},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5345807075500488},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.5208030939102173},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.5124804973602295},{"id":"https://openalex.org/C149227320","wikidata":"https://www.wikidata.org/wiki/Q884718","display_name":"Block diagram","level":2,"score":0.4819662272930145},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47907787561416626},{"id":"https://openalex.org/C85899133","wikidata":"https://www.wikidata.org/wiki/Q557211","display_name":"Active filter","level":3,"score":0.47618570923805237},{"id":"https://openalex.org/C21424316","wikidata":"https://www.wikidata.org/wiki/Q718621","display_name":"Chebyshev filter","level":2,"score":0.431276798248291},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.42332321405410767},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.4069581925868988},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.39360716938972473},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.3748881220817566},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2194596529006958},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.190714031457901},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.173036128282547},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1385849416255951},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.13490626215934753},{"id":"https://openalex.org/C39394816","wikidata":"https://www.wikidata.org/wiki/Q939318","display_name":"RC circuit","level":4,"score":0.11803832650184631},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10137948393821716},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08720433712005615},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126623501402","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126623501402","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1530114827","https://openalex.org/W1566916904","https://openalex.org/W1597620877","https://openalex.org/W1963910593","https://openalex.org/W1966121718","https://openalex.org/W1968530080","https://openalex.org/W1969423740","https://openalex.org/W1970203984","https://openalex.org/W1979337577","https://openalex.org/W1986439755","https://openalex.org/W1996651941","https://openalex.org/W2011064070","https://openalex.org/W2011485793","https://openalex.org/W2012976315","https://openalex.org/W2016260264","https://openalex.org/W2017776293","https://openalex.org/W2030848303","https://openalex.org/W2063719055","https://openalex.org/W2067021002","https://openalex.org/W2074153736","https://openalex.org/W2075735747","https://openalex.org/W2079488942","https://openalex.org/W2110998161","https://openalex.org/W2113493322","https://openalex.org/W2152168227","https://openalex.org/W2157578787","https://openalex.org/W2166282944","https://openalex.org/W2501261048","https://openalex.org/W2607377756","https://openalex.org/W3127324847"],"related_works":["https://openalex.org/W2355610251","https://openalex.org/W2496264392","https://openalex.org/W2558640508","https://openalex.org/W2073989621","https://openalex.org/W1552627364","https://openalex.org/W4307640255","https://openalex.org/W2493047131","https://openalex.org/W2146519261","https://openalex.org/W2140609601","https://openalex.org/W2041820660"],"abstract_inverted_index":{"In":[0],"this":[1],"study,":[2],"a":[3,11],"novel":[4],"DDCC-based":[5],"two-integrator-loop":[6],"universal":[7],"active-C":[8],"biquad":[9],"with":[10],"companding":[12],"process":[13],"scheme":[14],"is":[15,38,47],"proposed.":[16],"The":[17,30,42],"proposed":[18,60],"filter":[19,61,70,80],"employs":[20],"some":[21],"processing":[22],"blocks":[23],"such":[24,72],"as":[25,73],"integrators":[26],"and":[27,40,78,96,115],"summing":[28],"blocks.":[29],"use":[31],"of":[32,52,58,92,104],"the":[33,50,53,59,105,122,130,134],"block":[34],"diagram":[35],"design":[36],"procedure":[37],"attractive":[39],"systematic.":[41],"state":[43],"space":[44],"synthesis":[45],"technique":[46],"utilized":[48],"for":[49],"topology":[51],"integrator":[54],"design.":[55],"Several":[56],"advantages":[57],"are":[62,125,138],"briefly":[63],"expressed":[64],"as:":[65],"simultaneously":[66],"realizing":[67],"five":[68],"second-order":[69],"functions":[71],"low-pass,":[74],"high-pass,":[75],"band-pass,":[76],"all-pass":[77],"notch":[79],"responses;":[81],"offering":[82],"resistorless":[83],"realization;":[84],"dissipating":[85],"low":[86],"power;":[87],"having":[88],"electronic":[89],"tunability":[90],"feature":[91],"its":[93],"pole":[94],"frequency":[95,114],"quality":[97],"factor":[98],"orthogonally;":[99],"not":[100],"suffering":[101],"from":[102],"disadvantages":[103],"passive":[106],"element":[107],"matching":[108],"problems.":[109],"Some":[110],"simulation":[111,136],"results":[112,119,137],"including":[113],"time":[116],"domain":[117],"analysis":[118],"by":[120],"using":[121],"PSpice":[123],"program":[124],"carried":[126],"out":[127],"to":[128],"confirm":[129],"theoretical":[131],"ones.":[132],"All":[133],"obtained":[135],"discussed.":[139]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-08-05T07:39:15.569665","created_date":"2025-10-10T00:00:00"}
