{"id":"https://openalex.org/W4293216396","doi":"https://doi.org/10.1142/s0218126623500597","title":"A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency","display_name":"A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency","publication_year":2022,"publication_date":"2022-08-24","ids":{"openalex":"https://openalex.org/W4293216396","doi":"https://doi.org/10.1142/s0218126623500597"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126623500597","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126623500597","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5012748074","display_name":"Ravi Kumar","orcid":"https://orcid.org/0000-0002-4661-7589"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ravi Kumar","raw_affiliation_strings":["NSDCS Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, M.P. 453552, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NSDCS Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, M.P. 453552, India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089334609","display_name":"R. Nagulapalli","orcid":"https://orcid.org/0000-0003-0526-3232"},"institutions":[{"id":"https://openalex.org/I124261462","display_name":"Oxford Brookes University","ror":"https://ror.org/04v2twj65","country_code":"GB","type":"education","lineage":["https://openalex.org/I124261462"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Rajasekhar Nagulapalli","raw_affiliation_strings":["School of Engineering, Computing, and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering, Computing, and Mathematics, Oxford Brookes University, Wheatley Campus, Wheatley, Oxford, OX33 1HX, UK","institution_ids":["https://openalex.org/I124261462"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068792760","display_name":"Santosh Kumar Vishvakarma","orcid":"https://orcid.org/0000-0003-4223-0077"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Santosh Kumar Vishvakarma","raw_affiliation_strings":["NSDCS Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, M.P. 453552, India"],"raw_orcid":"https://orcid.org/0000-0003-4223-0077","affiliations":[{"raw_affiliation_string":"NSDCS Lab, Department of Electrical Engineering, Indian Institute of Technology, Indore, M.P. 453552, India","institution_ids":["https://openalex.org/I64295750"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5089334609"],"corresponding_institution_ids":["https://openalex.org/I124261462"],"apc_list":null,"apc_paid":null,"fwci":0.1767,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.45694205,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"32","issue":"04","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.9176011085510254},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.741699755191803},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6973116993904114},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.6612837910652161},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.6219441890716553},{"id":"https://openalex.org/keywords/delay-line-oscillator","display_name":"Delay line oscillator","score":0.570980429649353},{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.5276875495910645},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"Digitally controlled oscillator","score":0.5048802495002747},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47586601972579956},{"id":"https://openalex.org/keywords/variable-frequency-oscillator","display_name":"Variable-frequency oscillator","score":0.47220951318740845},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.44084393978118896},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4358745515346527},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.43522605299949646},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.42325571179389954},{"id":"https://openalex.org/keywords/vack\u00e1\u0159-oscillator","display_name":"Vack\u00e1\u0159 oscillator","score":0.41585439443588257},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3933447599411011},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.33305078744888306},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.3171505033969879},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2755976915359497},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2654951512813568},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19471287727355957}],"concepts":[{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.9176011085510254},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.741699755191803},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6973116993904114},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.6612837910652161},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.6219441890716553},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.570980429649353},{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.5276875495910645},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.5048802495002747},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47586601972579956},{"id":"https://openalex.org/C120164764","wikidata":"https://www.wikidata.org/wiki/Q705396","display_name":"Variable-frequency oscillator","level":4,"score":0.47220951318740845},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.44084393978118896},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4358745515346527},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.43522605299949646},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.42325571179389954},{"id":"https://openalex.org/C111657199","wikidata":"https://www.wikidata.org/wiki/Q2300256","display_name":"Vack\u00e1\u0159 oscillator","level":4,"score":0.41585439443588257},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3933447599411011},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.33305078744888306},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.3171505033969879},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2755976915359497},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2654951512813568},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19471287727355957}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126623500597","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126623500597","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7300000190734863}],"awards":[{"id":"https://openalex.org/G1883417697","display_name":null,"funder_award_id":"9(1)/2014-MDD","funder_id":"https://openalex.org/F4320321071","funder_display_name":"Department of Electronics and Information Technology, Ministry of Communications and Information Technology"}],"funders":[{"id":"https://openalex.org/F4320321071","display_name":"Department of Electronics and Information Technology, Ministry of Communications and Information Technology","ror":"https://ror.org/02z31cn83"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1566916904","https://openalex.org/W1995001961","https://openalex.org/W2015428081","https://openalex.org/W2029872673","https://openalex.org/W2114804139","https://openalex.org/W2116680714","https://openalex.org/W2126148071","https://openalex.org/W2145750057","https://openalex.org/W2163643591","https://openalex.org/W2467178995","https://openalex.org/W2768152238","https://openalex.org/W2775023910","https://openalex.org/W2783828345","https://openalex.org/W2785315525","https://openalex.org/W2922466273","https://openalex.org/W2973054452","https://openalex.org/W2979894602","https://openalex.org/W3212502668","https://openalex.org/W4221130393"],"related_works":["https://openalex.org/W2572239314","https://openalex.org/W1521697648","https://openalex.org/W4378390304","https://openalex.org/W2354924531","https://openalex.org/W1589246925","https://openalex.org/W2363002908","https://openalex.org/W2374234909","https://openalex.org/W3184559341","https://openalex.org/W2164559095","https://openalex.org/W4293216396"],"abstract_inverted_index":{"Phase":[0],"Locked":[1],"Loop":[2],"(PLL)":[3],"is":[4,17,36,51,101,116,139],"an":[5],"on-chip":[6],"clock":[7],"generator":[8],"for":[9,21,72,103],"timing-centric":[10],"electronic":[11],"systems.":[12],"Voltage":[13,92],"Controlled":[14],"Oscillator":[15],"(VCO)":[16],"the":[18,42,52,73,185],"key":[19],"element":[20],"high-performance":[22],"PLLs.":[23],"A":[24,126],"detailed":[25,123],"qualitative":[26],"explanation":[27],"has":[28,177],"been":[29,178],"given":[30,172],"to":[31,99,182],"describe":[32],"VCO":[33],"operation.":[34],"It":[35],"shown":[37],"from":[38,180,196],"simulation":[39,70,150],"results":[40,71,151],"that":[41,157],"variation":[43,63,85,162,167],"of":[44,56,128,135,163,168],"small":[45],"signal":[46],"transconductance":[47],"([Formula:":[48,60],"see":[49,61,82,88,137,143,160,193,198],"text])":[50,62],"main":[53],"dominant":[54],"source":[55],"frequency":[57,134,166],"and":[58,148,165],"gain":[59],"in":[64,86,118,141],"a":[65,112,122,171],"VCO.":[66],"In":[67],"this":[68,110,119],"work,":[69],"conventional":[74],"ring":[75,130],"oscillator":[76,131],"are":[77,152],"presented":[78],"which":[79],"demonstrates":[80],"[Formula:":[81,87,159],"text]":[83,89,161],"times":[84],"across":[90],"Process":[91],"Temperature":[93,175],"(PVT)":[94],"corners.":[95],"Such":[96],"huge":[97],"sensitivity":[98,176],"PVT":[100],"undesirable":[102],"high":[104],"bandwidth":[105],"PLL":[106],"design.":[107],"To":[108],"mitigate":[109],"sensitivity,":[111],"constant-gm":[113],"bias":[114],"circuit":[115],"proposed":[117,186],"paper,":[120],"with":[121,132],"mathematical":[124],"analysis.":[125],"prototype":[127],"4-stage":[129],"center":[133],"5[Formula:":[136],"text]GHz":[138],"developed":[140],"65[Formula:":[142],"text]nm":[144],"TSMC":[145],"CMOS":[146],"technology,":[147],"post-layout":[149],"carried":[153],"out.":[154],"Results":[155],"show":[156],"maximum":[158],"28%":[164],"17%":[169],"at":[170],"control":[173],"voltage.":[174],"decreased":[179],"19.3%":[181],"7%":[183],"using":[184],"biasing":[187],"technique.":[188],"Proposed":[189],"solution":[190],"consumes":[191],"2.4[Formula:":[192],"text]mW":[194],"power":[195,200],"1[Formula:":[197],"text]V":[199],"supply.":[201]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}