{"id":"https://openalex.org/W4290603417","doi":"https://doi.org/10.1142/s0218126623500391","title":"Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network","display_name":"Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network","publication_year":2022,"publication_date":"2022-08-08","ids":{"openalex":"https://openalex.org/W4290603417","doi":"https://doi.org/10.1142/s0218126623500391"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126623500391","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126623500391","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000944010","display_name":"Mangal Deep Gupta","orcid":"https://orcid.org/0000-0003-1213-3487"},"institutions":[{"id":"https://openalex.org/I4387154809","display_name":"ABES Engineering College","ror":"https://ror.org/04hp0cf98","country_code":null,"type":"education","lineage":["https://openalex.org/I4387154809"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mangal Deep Gupta","raw_affiliation_strings":["Department of Electronics and Communication Engineering, ABES Engineering College, Ghaziabad, Uttar Pradesh 201009, India"],"raw_orcid":"https://orcid.org/0000-0003-1213-3487","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, ABES Engineering College, Ghaziabad, Uttar Pradesh 201009, India","institution_ids":["https://openalex.org/I4387154809"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085107782","display_name":"R. K. Chauhan","orcid":"https://orcid.org/0000-0003-0291-0772"},"institutions":[{"id":"https://openalex.org/I2799532815","display_name":"Madan Mohan Malaviya University of Technology","ror":"https://ror.org/04h1w2j35","country_code":"IN","type":"education","lineage":["https://openalex.org/I2799532815"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. K. Chauhan","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur 273016, Uttar Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur 273016, Uttar Pradesh, India","institution_ids":["https://openalex.org/I2799532815"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073813650","display_name":"Sandeep Gulia","orcid":"https://orcid.org/0000-0001-5756-0453"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sandeep Gulia","raw_affiliation_strings":["School of Engineering and Technology, Sushant University, Gurugram 122003, Haryana, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering and Technology, Sushant University, Gurugram 122003, Haryana, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5000944010"],"corresponding_institution_ids":["https://openalex.org/I4387154809"],"apc_list":null,"apc_paid":null,"fwci":0.5249,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.70385358,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"32","issue":"03","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11017","display_name":"Chaos-based Image/Signal Encryption","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6812125444412231},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.6179172992706299},{"id":"https://openalex.org/keywords/pseudorandom-number-generator","display_name":"Pseudorandom number generator","score":0.5203527808189392},{"id":"https://openalex.org/keywords/random-number-generation","display_name":"Random number generation","score":0.5108949542045593},{"id":"https://openalex.org/keywords/linear-congruential-generator","display_name":"Linear congruential generator","score":0.49349749088287354},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.48024705052375793},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4609028100967407},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37653404474258423},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.303128719329834},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.26406949758529663}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6812125444412231},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.6179172992706299},{"id":"https://openalex.org/C140642157","wikidata":"https://www.wikidata.org/wiki/Q1623338","display_name":"Pseudorandom number generator","level":2,"score":0.5203527808189392},{"id":"https://openalex.org/C201866948","wikidata":"https://www.wikidata.org/wiki/Q228206","display_name":"Random number generation","level":2,"score":0.5108949542045593},{"id":"https://openalex.org/C141890704","wikidata":"https://www.wikidata.org/wiki/Q1190228","display_name":"Linear congruential generator","level":3,"score":0.49349749088287354},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.48024705052375793},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4609028100967407},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37653404474258423},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.303128719329834},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.26406949758529663},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126623500391","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126623500391","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.44999998807907104,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1483874305","https://openalex.org/W1991809541","https://openalex.org/W2067198933","https://openalex.org/W2145779853","https://openalex.org/W2150370646","https://openalex.org/W2284010485","https://openalex.org/W2287502722","https://openalex.org/W2314197416","https://openalex.org/W2561675875","https://openalex.org/W2590132587","https://openalex.org/W2604042328","https://openalex.org/W2604813584","https://openalex.org/W2773862155","https://openalex.org/W2783598248","https://openalex.org/W2789349233","https://openalex.org/W2807345858","https://openalex.org/W2895956485","https://openalex.org/W2901295393","https://openalex.org/W2901370871","https://openalex.org/W2902123208","https://openalex.org/W2914483908","https://openalex.org/W2927872402","https://openalex.org/W2968111791","https://openalex.org/W2980732620","https://openalex.org/W2989697261","https://openalex.org/W3029791221","https://openalex.org/W3081287854","https://openalex.org/W3112391664","https://openalex.org/W3151653951","https://openalex.org/W3186019728","https://openalex.org/W3198332764"],"related_works":["https://openalex.org/W2069525877","https://openalex.org/W3148086566","https://openalex.org/W2059561929","https://openalex.org/W1965136003","https://openalex.org/W2702071719","https://openalex.org/W3023270287","https://openalex.org/W1543916906","https://openalex.org/W4312710304","https://openalex.org/W1499214257","https://openalex.org/W2060398071"],"abstract_inverted_index":{"A":[0],"new":[1],"method":[2],"for":[3,242],"the":[4,33,36,46,58,66,78,87,101,119,137,146,156,173,178,207,236],"generation":[5],"of":[6,35,38,90,108,121,177,206,218],"pseudo-random":[7,59,91],"bits,":[8],"based":[9,117],"on":[10,118,193],"a":[11],"coupled-linear":[12],"congruential":[13,41],"generator":[14,42,61],"(CLCG)":[15],"and":[16,73,141,150,190,202],"two":[17,125],"multistage":[18,47,128],"variable":[19,48,126],"seeds":[20,37,49,127],"linear":[21,40],"feedback":[22],"shift":[23],"registers":[24],"(LFSRs)":[25],"is":[26,110,116,134,165],"presented.":[27],"The":[28,51,130,160,182,204,231],"proposed":[29,52,111,183,208,237],"algorithm":[30],"dynamically":[31],"changes":[32],"value":[34],"each":[39],"(LCG)":[43],"by":[44,136],"utilizing":[45],"LFSR.":[50],"approach":[53],"exhibits":[54],"several":[55],"advantages":[56],"over":[57],"bit":[60,92],"(PRBG)":[62],"methods":[63],"presented":[64],"in":[65,112,168,210],"literature.":[67],"It":[68,115],"provides":[69],"low":[70,222],"hardware":[71],"complexity":[72],"high-security":[74],"strength":[75],"while":[76,153],"maintaining":[77],"minimum":[79],"critical":[80,102],"path":[81,103],"delay.":[82],"Moreover,":[83],"this":[84,113,169,211],"design":[85],"generates":[86],"maximum":[88],"length":[89],"sequence":[93,234],"with":[94,124,224],"uniform":[95],"clock":[96,161],"latency.":[97],"Furthermore,":[98],"to":[99,171,228],"improve":[100],"delay,":[104],"one":[105],"more":[106],"architecture":[107,209],"PRBG":[109,180],"work.":[114],"combination":[120],"coupled":[122],"modified-LCG":[123],"LFSRs.":[129],"modified":[131],"LCG":[132],"block":[133],"designed":[135],"two-operand":[138],"modulo":[139,148],"adder":[140,149],"XOR":[142],"gate,":[143],"rather":[144],"than":[145],"three-operands":[147],"shifting":[151],"operation,":[152],"it":[154],"maintains":[155],"same":[157],"security":[158],"strength.":[159],"gating":[162],"network":[163],"(CGN)":[164],"also":[166],"used":[167],"work":[170],"minimize":[172],"dynamic":[174],"power":[175,223],"dissipation":[176],"overall":[179],"architecture.":[181],"architectures":[184],"are":[185],"implemented":[186],"using":[187,245],"Verilog":[188],"HDL":[189],"further":[191],"prototyped":[192],"commercially":[194],"available":[195],"field-programmable":[196],"gate":[197],"array":[198],"(FPGA)":[199],"devices":[200],"Virtex-5":[201],"Virtex-7.":[203],"realization":[205],"FPGA":[212],"device":[213],"accomplishes":[214],"an":[215],"improved":[216],"speed":[217],"PRBG,":[219],"which":[220],"consumes":[221],"high":[225],"randomness":[226,243],"compared":[227],"existing":[229],"techniques.":[230],"generated":[232],"binary":[233],"from":[235],"algorithms":[238],"has":[239],"been":[240],"verified":[241],"tests":[244],"NIST":[246],"statistical":[247],"test":[248],"suites.":[249]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}