{"id":"https://openalex.org/W4281918137","doi":"https://doi.org/10.1142/s0218126622502929","title":"Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder","display_name":"Design of Power, Area and Delay Optimized Direct Digital Synthesizer Using Modified 32-Bit Square Root Carry Select Adder","publication_year":2022,"publication_date":"2022-06-09","ids":{"openalex":"https://openalex.org/W4281918137","doi":"https://doi.org/10.1142/s0218126622502929"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126622502929","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622502929","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077004352","display_name":"Raju Ganna","orcid":"https://orcid.org/0000-0002-2264-139X"},"institutions":[{"id":"https://openalex.org/I110360157","display_name":"Lovely Professional University","ror":"https://ror.org/00et6q107","country_code":"IN","type":"education","lineage":["https://openalex.org/I110360157"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Raju Ganna","raw_affiliation_strings":["VLSI design SEEE, School of Electronics & Electrical Engineering, Lovely Professional University, Punjab, India"],"affiliations":[{"raw_affiliation_string":"VLSI design SEEE, School of Electronics & Electrical Engineering, Lovely Professional University, Punjab, India","institution_ids":["https://openalex.org/I110360157"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091376555","display_name":"Shanky Saxena","orcid":"https://orcid.org/0000-0002-3100-6486"},"institutions":[{"id":"https://openalex.org/I110360157","display_name":"Lovely Professional University","ror":"https://ror.org/00et6q107","country_code":"IN","type":"education","lineage":["https://openalex.org/I110360157"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shanky Saxena","raw_affiliation_strings":["VLSI Design, Lovely Professional University, Punjab, India"],"affiliations":[{"raw_affiliation_string":"VLSI Design, Lovely Professional University, Punjab, India","institution_ids":["https://openalex.org/I110360157"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023557010","display_name":"Govind Singh Patel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Govind Singh Patel","raw_affiliation_strings":["E&TC Department, SITCOE, Yadrav, Kolhapur, Maharashtra, India"],"affiliations":[{"raw_affiliation_string":"E&TC Department, SITCOE, Yadrav, Kolhapur, Maharashtra, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5077004352"],"corresponding_institution_ids":["https://openalex.org/I110360157"],"apc_list":null,"apc_paid":null,"fwci":0.2444,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.46055031,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":"31","issue":"17","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9489033818244934},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6516675353050232},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.6355472207069397},{"id":"https://openalex.org/keywords/carry","display_name":"Carry (investment)","score":0.49227991700172424},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.44530078768730164},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44505369663238525},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.4390813708305359},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.43103283643722534},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36873751878738403},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3504266142845154},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20250001549720764},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14951327443122864},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1385757029056549},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.09424915909767151}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9489033818244934},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6516675353050232},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.6355472207069397},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.49227991700172424},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.44530078768730164},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44505369663238525},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4390813708305359},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.43103283643722534},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36873751878738403},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3504266142845154},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20250001549720764},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14951327443122864},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1385757029056549},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.09424915909767151},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126622502929","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622502929","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2588521942","https://openalex.org/W2728308784","https://openalex.org/W2783670694","https://openalex.org/W2790284972","https://openalex.org/W2901965504","https://openalex.org/W2906666878","https://openalex.org/W2911935832","https://openalex.org/W2912661429","https://openalex.org/W2944702668","https://openalex.org/W2972216239","https://openalex.org/W3008837131","https://openalex.org/W3016137691","https://openalex.org/W3023820769","https://openalex.org/W3164956630","https://openalex.org/W3166728167","https://openalex.org/W3198416101","https://openalex.org/W3215536867","https://openalex.org/W4237488480","https://openalex.org/W4239978242"],"related_works":["https://openalex.org/W2064215635","https://openalex.org/W986131379","https://openalex.org/W1976039195","https://openalex.org/W2605666407","https://openalex.org/W1584617340","https://openalex.org/W2950842282","https://openalex.org/W2157955791","https://openalex.org/W2003324248","https://openalex.org/W2127980940","https://openalex.org/W2532181444"],"abstract_inverted_index":{"Improved":[0],"speed,":[1],"reduced":[2,4,7],"delay,":[3,225],"size":[5],"and":[6,52,81,179,227,274,290,303],"power":[8,149,265,308],"are":[9,166,284],"the":[10,25,48,67,79,87,98,110,124,128,132,135,152,159,177,181,184,187,195,231,236,242,245,249,264,294,297,311,321],"most":[11,26,30],"important":[12,27],"requirements":[13],"of":[14,24,39,69,72,117,134,154,164,183,207,223],"integrated":[15],"circuits.":[16],"The":[17,37,56,141,204,215,306],"carry":[18,74,92],"select":[19,93],"adder":[20,94,136],"(CSA)":[21],"is":[22,62,123,137,191,209,253,266,276,314],"one":[23],"adders":[28,41,75],"in":[29,60,109,127,158,221,230],"data":[31],"processors":[32],"for":[33,77],"performing":[34],"arithmetic":[35],"operations.":[36],"speed":[38,51,133,178],"parallel":[40],"can":[42],"be":[43,256,279,318],"enhanced":[44,138],"CSA,":[45],"which":[46,283],"widens":[47],"area":[49,64,246],"to":[50,66,96,114,151,171,175,235,241,255,278,317],"eliminates":[53],"propagation":[54],"delays.":[55],"major":[57],"problem":[58],"faced":[59],"CSA":[61,145],"inefficient":[63],"due":[65,113,150],"usage":[68],"multiple":[70],"pairs":[71],"Ripple":[73],"(RCAs)":[76],"generating":[78],"sums":[80],"carry.":[82],"This":[83],"research":[84],"paper":[85],"proposes":[86],"modified":[88],"32-bit":[89],"square":[90,143],"root":[91,144],"(MSCSLA)":[95],"improve":[97,176],"direct":[99],"digital":[100,111],"synthesizer\u2019s":[101],"performance":[102,229],"(DDS).":[103],"DDS":[104,129,208,232],"plays":[105],"an":[106],"effective":[107],"role":[108],"system":[112],"its":[115],"ability":[116],"broad":[118],"frequency":[119,292],"generation.":[120],"Phase":[121],"accumulator":[122],"main":[125],"component":[126],"synthesizer,":[130],"where":[131],"through":[139],"MSCSLA.":[140],"general":[142],"still":[146],"consumes":[147],"more":[148,155],"assembly":[153],"RCAs.":[156],"Hence,":[157],"proposed":[160,250,298,312],"approach,":[161],"certain":[162],"sets":[163],"RCAs":[165],"replaced":[167],"with":[168,293],"BEC1":[169],"(Binary":[170],"excess":[172],"1":[173],"convertor)":[174],"reduce":[180],"delay":[182,275,289,302],"adder.":[185],"Finally,":[186],"continuous":[188],"sinusoidal":[189],"waveform":[190],"attained":[192,254,277,316],"by":[193,198,248,310],"attenuating":[194],"high-frequency":[196],"components":[197],"adopting":[199],"a":[200],"low":[201],"pass":[202],"filter.":[203],"entire":[205],"structure":[206],"designed":[210],"using":[211],"Xilinx":[212],"Verilog":[213],"coding.":[214],"Simulation":[216],"result":[217],"shows":[218],"better":[219],"outcomes":[220],"terms":[222],"area,":[224],"power,":[226],"high":[228],"synthesizer":[233],"compared":[234,240],"existing":[237,243,295,322],"CSAs.":[238],"When":[239,287],"adders,":[244],"occupied":[247],"MSCSLA":[251],"model":[252,299,313],"636[Formula:":[257],"see":[258,260,270,272,281],"text][Formula:":[259,271],"text]m":[261],"2":[262],",":[263],"achieved":[267],"as":[268],"50.125[Formula:":[269],"text]W":[273],"1.280[Formula:":[280],"text]ns,":[282],"comparatively":[285],"less.":[286],"comparing":[288],"maximum":[291,304],"techniques,":[296],"obtained":[300],"minimum":[301],"frequency.":[305],"overall":[307],"consumption":[309],"also":[315],"lower":[319],"than":[320],"techniques.":[323]},"counts_by_year":[{"year":2025,"cited_by_count":3}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
