{"id":"https://openalex.org/W4281286200","doi":"https://doi.org/10.1142/s0218126622502681","title":"A Novel Design of High-Performance Hybrid Multiplier","display_name":"A Novel Design of High-Performance Hybrid Multiplier","publication_year":2022,"publication_date":"2022-05-23","ids":{"openalex":"https://openalex.org/W4281286200","doi":"https://doi.org/10.1142/s0218126622502681"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126622502681","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622502681","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083657017","display_name":"Jugal Kishore Bhandari","orcid":"https://orcid.org/0000-0002-8176-7224"},"institutions":[{"id":"https://openalex.org/I110360157","display_name":"Lovely Professional University","ror":"https://ror.org/00et6q107","country_code":"IN","type":"education","lineage":["https://openalex.org/I110360157"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Jugal Kishore Bhandari","raw_affiliation_strings":["School of Electronics and Electrical Engineering, Lovely Professional University, Jalandhar 144411, Punjab, India"],"raw_orcid":"https://orcid.org/0000-0002-8176-7224","affiliations":[{"raw_affiliation_string":"School of Electronics and Electrical Engineering, Lovely Professional University, Jalandhar 144411, Punjab, India","institution_ids":["https://openalex.org/I110360157"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088337404","display_name":"Yogesh Kumar Verma","orcid":"https://orcid.org/0000-0003-4145-7202"},"institutions":[{"id":"https://openalex.org/I110360157","display_name":"Lovely Professional University","ror":"https://ror.org/00et6q107","country_code":"IN","type":"education","lineage":["https://openalex.org/I110360157"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Yogesh Kumar Verma","raw_affiliation_strings":["School of Electronics and Electrical Engineering, Lovely Professional University, Jalandhar 144411, Punjab, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics and Electrical Engineering, Lovely Professional University, Jalandhar 144411, Punjab, India","institution_ids":["https://openalex.org/I110360157"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032424551","display_name":"Laxman Singh","orcid":"https://orcid.org/0000-0003-3297-6625"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Laxman Singh","raw_affiliation_strings":["Department of Electronics & Communication Engineering, Noida Institute of Engineering and Technology, Uttar Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics & Communication Engineering, Noida Institute of Engineering and Technology, Uttar Pradesh, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028498726","display_name":"Santosh Kumar Gupta","orcid":"https://orcid.org/0000-0003-4235-9065"},"institutions":[{"id":"https://openalex.org/I152869788","display_name":"Motilal Nehru National Institute of Technology","ror":"https://ror.org/04dp7tp96","country_code":"IN","type":"education","lineage":["https://openalex.org/I152869788"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Santosh Kumar Gupta","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Prayagraj, Allahabad, Prayagraj 211004, Uttar Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Prayagraj, Allahabad, Prayagraj 211004, Uttar Pradesh, India","institution_ids":["https://openalex.org/I152869788"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5083657017"],"corresponding_institution_ids":["https://openalex.org/I110360157"],"apc_list":null,"apc_paid":null,"fwci":0.2976,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.47491061,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"31","issue":"15","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.8909249901771545},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6477222442626953},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.5831043720245361},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.463248610496521},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.42264798283576965},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.4223184883594513},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.3780018091201782},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3533514738082886},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10430905222892761}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.8909249901771545},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6477222442626953},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.5831043720245361},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.463248610496521},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.42264798283576965},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.4223184883594513},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3780018091201782},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3533514738082886},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10430905222892761},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126622502681","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622502681","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2044586161","https://openalex.org/W2087134685","https://openalex.org/W2124651102","https://openalex.org/W2557882536","https://openalex.org/W2615476531","https://openalex.org/W2623290133","https://openalex.org/W2765751199","https://openalex.org/W2799283557","https://openalex.org/W2904983908","https://openalex.org/W2912744753","https://openalex.org/W2999244910","https://openalex.org/W3004524066","https://openalex.org/W3010038952","https://openalex.org/W3018565930","https://openalex.org/W4213324576"],"related_works":["https://openalex.org/W2901668507","https://openalex.org/W1999766726","https://openalex.org/W2807717303","https://openalex.org/W3196607417","https://openalex.org/W2433005626","https://openalex.org/W4386229492","https://openalex.org/W4235554932","https://openalex.org/W4312638859","https://openalex.org/W4256198279","https://openalex.org/W31956781"],"abstract_inverted_index":{"In":[0,33,89],"this":[1,34,90],"brief,":[2],"a":[3,15,38,132],"novel":[4],"design":[5],"of":[6,17,21,41,53],"hybrid":[7,12,43,77,117,121,137,153],"multiplier":[8,13,44,78,122,138],"is":[9,14,56,71,107,139],"proposed.":[10],"The":[11,23,51,68,119],"combination":[16],"two":[18,92],"different":[19,93],"types":[20],"multipliers.":[22,32,50,154],"latest":[24],"computing":[25],"systems":[26],"require":[27],"low-power,":[28],"area,":[29],"and":[30,48,144],"delay":[31,113],"work,":[35],"we":[36],"extend":[37],"new":[39],"idea":[40],"high-performance":[42],"by":[45,58,73],"using":[46,126,131],"Wallace\u2013Dadda":[47],"Vedic":[49],"addition":[52],"partial":[54,82],"products":[55,83],"done":[57],"dividing":[59],"them":[60],"into":[61,86],"smaller":[62],"groups":[63],"to":[64,97,109,150],"obtain":[65],"faster":[66],"results.":[67],"proposed":[69,116,120],"method":[70],"illustrated":[72],"designing":[74],"an":[75],"8-bit":[76],"in":[79,114],"which":[80],"the":[81,101,115,127,151],"are":[84,95],"divided":[85],"four":[87],"subgroups.":[88],"analysis,":[91],"multipliers":[94],"applied":[96],"alternative":[98],"groups.":[99],"Finally,":[100],"carry":[102,111],"look":[103],"ahead":[104],"adder":[105],"(CLA)":[106],"used":[108],"reduce":[110],"propagation":[112],"multiplier.":[118],"has":[123],"been":[124],"synthesized":[125],"Cadence":[128],"virtuoso":[129],"tool":[130],"45-nm":[133],"CMOS":[134],"technology.":[135],"This":[136],"faster,":[140],"consumes":[141],"less":[142,146],"power,":[143],"occupies":[145],"area":[147],"as":[148],"compared":[149],"conventional":[152]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2}],"updated_date":"2026-07-18T07:39:51.176621","created_date":"2025-10-10T00:00:00"}
