{"id":"https://openalex.org/W4229441133","doi":"https://doi.org/10.1142/s0218126622502176","title":"Design and Implementation of Time-Frequency Distributions for Real-Time Applications Using Field Programmable Gate Array","display_name":"Design and Implementation of Time-Frequency Distributions for Real-Time Applications Using Field Programmable Gate Array","publication_year":2022,"publication_date":"2022-05-09","ids":{"openalex":"https://openalex.org/W4229441133","doi":"https://doi.org/10.1142/s0218126622502176"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126622502176","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622502176","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101902812","display_name":"B. Murali Krishna","orcid":null},"institutions":[{"id":"https://openalex.org/I142809039","display_name":"Jawaharlal Nehru Technological University, Kakinada","ror":"https://ror.org/05s9t8c95","country_code":"IN","type":"education","lineage":["https://openalex.org/I142809039"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"B. Murali Krishna","raw_affiliation_strings":["Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, Andhra Pradesh 534101, India","Electronics and Communication Department, Jawaharlal Nehru Technological University Kakinada, Kakinada, Andhra Pradesh 533003, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, Andhra Pradesh 534101, India","institution_ids":[]},{"raw_affiliation_string":"Electronics and Communication Department, Jawaharlal Nehru Technological University Kakinada, Kakinada, Andhra Pradesh 533003, India","institution_ids":["https://openalex.org/I142809039"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067288376","display_name":"B. T. Krishna","orcid":"https://orcid.org/0000-0002-8316-7310"},"institutions":[{"id":"https://openalex.org/I142809039","display_name":"Jawaharlal Nehru Technological University, Kakinada","ror":"https://ror.org/05s9t8c95","country_code":"IN","type":"education","lineage":["https://openalex.org/I142809039"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B. T. Krishna","raw_affiliation_strings":["Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, Andhra Pradesh 534101, India","Electronics and Communication Department, Jawaharlal Nehru Technological University Kakinada, Kakinada, Andhra Pradesh 533003, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, Andhra Pradesh 534101, India","institution_ids":[]},{"raw_affiliation_string":"Electronics and Communication Department, Jawaharlal Nehru Technological University Kakinada, Kakinada, Andhra Pradesh 533003, India","institution_ids":["https://openalex.org/I142809039"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066949652","display_name":"K. Babulu","orcid":null},"institutions":[{"id":"https://openalex.org/I10874241","display_name":"Jawaharlal Nehru Technological University, Hyderabad","ror":"https://ror.org/002tchr49","country_code":"IN","type":"education","lineage":["https://openalex.org/I10874241"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. Babulu","raw_affiliation_strings":["Electronics and Communication Department, Jawaharlal Nehru Technological University Vizianagaram, Vizianagaram, Andhra Pradesh 535003, India"],"affiliations":[{"raw_affiliation_string":"Electronics and Communication Department, Jawaharlal Nehru Technological University Vizianagaram, Vizianagaram, Andhra Pradesh 535003, India","institution_ids":["https://openalex.org/I10874241"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101902812"],"corresponding_institution_ids":["https://openalex.org/I142809039"],"apc_list":null,"apc_paid":null,"fwci":0.6025,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.64531837,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"31","issue":"12","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10220","display_name":"Machine Fault Diagnosis Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10220","display_name":"Machine Fault Diagnosis Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11447","display_name":"Blind Source Separation Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7966636419296265},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7471921443939209},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.6727805137634277},{"id":"https://openalex.org/keywords/time\u2013frequency-analysis","display_name":"Time\u2013frequency analysis","score":0.5355271100997925},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.47561198472976685},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4755092263221741},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43786153197288513},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41255396604537964},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.33039379119873047},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14889854192733765},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0736246109008789},{"id":"https://openalex.org/keywords/radar","display_name":"Radar","score":0.07319644093513489}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7966636419296265},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7471921443939209},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.6727805137634277},{"id":"https://openalex.org/C142433447","wikidata":"https://www.wikidata.org/wiki/Q7806653","display_name":"Time\u2013frequency analysis","level":3,"score":0.5355271100997925},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.47561198472976685},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4755092263221741},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43786153197288513},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41255396604537964},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.33039379119873047},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14889854192733765},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0736246109008789},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.07319644093513489}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126622502176","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622502176","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W257439581","https://openalex.org/W2008144830","https://openalex.org/W2015655942","https://openalex.org/W2024753239","https://openalex.org/W2047264647","https://openalex.org/W2049588903","https://openalex.org/W2067530554","https://openalex.org/W2097780146","https://openalex.org/W2098744771","https://openalex.org/W2100240379","https://openalex.org/W2110017348","https://openalex.org/W2120847449","https://openalex.org/W2126730305","https://openalex.org/W2165760083","https://openalex.org/W2165878107","https://openalex.org/W2303253908","https://openalex.org/W2904538846","https://openalex.org/W2996317053","https://openalex.org/W3005111731"],"related_works":["https://openalex.org/W4327521644","https://openalex.org/W2111241003","https://openalex.org/W2978884468","https://openalex.org/W2168413811","https://openalex.org/W2005846134","https://openalex.org/W2387264083","https://openalex.org/W2604877941","https://openalex.org/W1669114967","https://openalex.org/W2390885485","https://openalex.org/W2362523726"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"time-frequency":[3],"distributions":[4],"(TFDs)":[5],"and":[6,67,103,127,136],"their":[7],"hardware":[8,58,155],"implementation":[9,59],"on":[10,129,158],"FPGA":[11,159],"are":[12,15,35,97,122,141],"presented.":[13],"TFDs":[14,61,102],"evolved":[16],"due":[17],"to":[18,49,75,99,145],"disadvantage":[19],"of":[20,44,60,83,114,153],"Fourier":[21],"Transform":[22],"(FT),":[23],"which":[24],"cannot":[25],"provide":[26],"time":[27,50],"information":[28,40],"in":[29,37,116],"spectrum":[30],"representation.":[31,92],"Time-Frequency":[32],"Representations":[33],"(TFRs)":[34],"helpful":[36],"providing":[38],"simultaneous":[39],"about":[41],"spectral":[42],"contents":[43],"a":[45,137,151],"signal":[46,91],"with":[47,57,160],"respect":[48],"period":[51],"axis.":[52],"The":[53,93],"major":[54],"problem":[55],"associated":[56],"is":[62,73,86,109],"limited":[63],"on-board":[64],"memory.":[65],"Forward":[66],"backward":[68],"register":[69,79,82,95],"allocation":[70],"method":[71],"(FBRA)":[72],"employed":[74],"obtain":[76],"the":[77,89,100,112,120,147],"optimum":[78],"occupation.":[80],"A":[81,132],"length":[84],"32-bit":[85],"considered":[87],"for":[88,164],"input":[90,144],"stored":[94],"values":[96],"applied":[98],"proposed":[101],"computed":[104],"using":[105,124],"real-time":[106,133,166],"hardware.":[107],"FBRA":[108],"implemented":[110,128],"during":[111],"computation":[113],"FFT":[115],"all":[117],"TFDs.":[118,149],"All":[119],"transforms":[121],"modeled":[123],"Verilog":[125],"code":[126],"SPARTA-6":[130],"FPGA.":[131],"ECG,":[134],"earthquake":[135],"quad":[138],"chirp":[139],"signals":[140],"taken":[142],"as":[143],"test":[146],"designed":[148],"Finally,":[150],"comparison":[152],"different":[154],"resources":[156],"utilized":[157],"earlier":[161],"conventional":[162],"methods":[163],"better":[165],"applications":[167],"was":[168],"made.":[169]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
