{"id":"https://openalex.org/W4297983419","doi":"https://doi.org/10.1142/s0218126622400096","title":"Transistor-Level Radiation Hardening by Design Techniques in Complex Gates","display_name":"Transistor-Level Radiation Hardening by Design Techniques in Complex Gates","publication_year":2022,"publication_date":"2022-09-30","ids":{"openalex":"https://openalex.org/W4297983419","doi":"https://doi.org/10.1142/s0218126622400096"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126622400096","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622400096","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049423875","display_name":"Bruno T. Ferraz","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Bruno T. Ferraz","raw_affiliation_strings":["Center for Technological Development, Federal University of Pelotas, Rua Gomes Carneiro, 1, Pelotas, Rio Grande do Sul, 96010-900, Brazil"],"affiliations":[{"raw_affiliation_string":"Center for Technological Development, Federal University of Pelotas, Rua Gomes Carneiro, 1, Pelotas, Rio Grande do Sul, 96010-900, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050032751","display_name":"Henrique Kessler","orcid":"https://orcid.org/0000-0002-1840-3794"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Henrique Kessler","raw_affiliation_strings":["Center for Technological Development, Federal University of Pelotas, Rua Gomes Carneiro, 1, Pelotas, Rio Grande do Sul, 96010-900, Brazil"],"affiliations":[{"raw_affiliation_string":"Center for Technological Development, Federal University of Pelotas, Rua Gomes Carneiro, 1, Pelotas, Rio Grande do Sul, 96010-900, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010001207","display_name":"Vin\u00edcius Valduga de Almeida Camargo","orcid":"https://orcid.org/0000-0003-2006-3642"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vin\u00edcius V. A. Camargo","raw_affiliation_strings":["Center for Technological Development, Federal University of Pelotas, Rua Gomes Carneiro, 1, Pelotas, Rio Grande do Sul, 96010-900, Brazil"],"affiliations":[{"raw_affiliation_string":"Center for Technological Development, Federal University of Pelotas, Rua Gomes Carneiro, 1, Pelotas, Rio Grande do Sul, 96010-900, Brazil","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5049423875"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.1829,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.47870128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"31","issue":"18","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7890836000442505},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6198068261146545},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5920761227607727},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.576689600944519},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5657458305358887},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.554573655128479},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4976041615009308},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.49528947472572327},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4772450923919678},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4722042977809906},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.464865505695343},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4482017159461975},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4257556200027466},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.424612820148468},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4196700155735016},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.38756492733955383},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20967727899551392},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17904025316238403},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10255298018455505}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7890836000442505},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6198068261146545},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5920761227607727},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.576689600944519},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5657458305358887},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.554573655128479},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4976041615009308},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.49528947472572327},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4772450923919678},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4722042977809906},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.464865505695343},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4482017159461975},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4257556200027466},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.424612820148468},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4196700155735016},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.38756492733955383},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20967727899551392},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17904025316238403},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10255298018455505},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126622400096","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126622400096","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1571320244","https://openalex.org/W1966897032","https://openalex.org/W2000038726","https://openalex.org/W2004047298","https://openalex.org/W2018989845","https://openalex.org/W2030501553","https://openalex.org/W2036472714","https://openalex.org/W2048751700","https://openalex.org/W2071068906","https://openalex.org/W2073564999","https://openalex.org/W2088115909","https://openalex.org/W2114556285","https://openalex.org/W2115516668","https://openalex.org/W2116549540","https://openalex.org/W2132620026","https://openalex.org/W2141068710","https://openalex.org/W2141585946","https://openalex.org/W2144270672","https://openalex.org/W2168860942","https://openalex.org/W2343967503","https://openalex.org/W2418937170","https://openalex.org/W2772187138","https://openalex.org/W2887645449","https://openalex.org/W2912161419","https://openalex.org/W2959662934","https://openalex.org/W2975091363","https://openalex.org/W3004834510","https://openalex.org/W3036677689","https://openalex.org/W3134774603","https://openalex.org/W3208994880"],"related_works":["https://openalex.org/W2168324060","https://openalex.org/W2186697267","https://openalex.org/W3021239402","https://openalex.org/W2152533674","https://openalex.org/W2169337913","https://openalex.org/W2991771859","https://openalex.org/W2166506797","https://openalex.org/W2131471893","https://openalex.org/W1513412524","https://openalex.org/W2006855068"],"abstract_inverted_index":{"Single":[0],"Event":[1],"Transients":[2],"(SETs)":[3],"have":[4,136],"become":[5],"a":[6,83,92,166,176],"major":[7],"reliability":[8],"concern":[9],"for":[10],"integrated":[11],"circuits":[12,25],"used":[13,117,128],"in":[14,46,158],"critical":[15,199],"applications.":[16],"Research":[17],"to":[18,37,69,87,118,129,164,182],"improve":[19,147],"the":[20,34,38,58,71,103,120,140],"radiation":[21],"robustness":[22,101,149],"of":[23,60,78,95,102,142,175],"digital":[24],"has":[26,162],"been":[27],"conducted,":[28],"assessing":[29],"all":[30],"abstraction":[31],"levels":[32],"(from":[33],"device":[35],"up":[36,181],"system).":[39],"This":[40],"study":[41],"evaluates":[42],"transistor-level":[43],"radiation-hardened":[44],"techniques":[45],"combinational":[47,72,159],"logic,":[48],"such":[49],"as":[50],"transistor":[51],"folding,":[52],"sizing":[53],"and":[54,65,123,204],"reordering.":[55],"In":[56],"addition,":[57],"efficiency":[59],"using":[61,156],"supergates,":[62],"including":[63],"series-parallel":[64],"non-series-parallel":[66],"CMOS":[67],"structures,":[68],"harden":[70],"logic":[73,84,105,143,160,178],"is":[74,89,98],"discussed.":[75],"The":[76,100,113,170],"dependence":[77],"input":[79],"signals":[80],"probability":[81],"on":[82,193],"cell":[85],"susceptibility":[86],"SET":[88,111,121,186],"assessed.":[90],"Moreover,":[91],"new":[93],"concept":[94],"electrical":[96,125],"masking":[97],"introduced.":[99],"investigated":[104],"cells":[106],"was":[107,116,127],"evaluated":[108],"regarding":[109,189],"their":[110],"rate.":[112],"CREME96":[114],"tool":[115],"generate":[119],"rates,":[122],"an":[124,190],"model":[126],"perform":[130],"particle":[131],"hit":[132],"simulations.":[133],"Obtained":[134],"results":[135],"indicated":[137],"that":[138],"modifying":[139],"structure":[141],"gates":[144],"can":[145],"substantially":[146],"circuit":[148],"without":[150],"necessarily":[151],"worsening":[152],"its":[153],"performance.":[154],"Besides,":[155],"supergates":[157],"design":[161],"demonstrated":[163],"be":[165],"promising":[167],"hardening":[168],"strategy.":[169],"most":[171],"robust":[172],"supergate":[173],"implementation":[174],"five-input":[177],"function":[179],"provided":[180],"[Formula:":[183],"see":[184,202,208],"text]":[185],"rate":[187],"reduction":[188],"approach":[191],"based":[192],"standard":[194],"cells,":[195],"along":[196],"with":[197],"lower":[198],"delay":[200],"([Formula:":[201,207],"text])":[203],"average":[205],"power":[206],"text]).":[209]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
