{"id":"https://openalex.org/W3096394083","doi":"https://doi.org/10.1142/s0218126621501425","title":"Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability","display_name":"Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability","publication_year":2020,"publication_date":"2020-10-28","ids":{"openalex":"https://openalex.org/W3096394083","doi":"https://doi.org/10.1142/s0218126621501425","mag":"3096394083"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126621501425","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126621501425","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101823321","display_name":"R. Manoj Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I100887729","display_name":"Andhra University","ror":"https://ror.org/049skhf47","country_code":"IN","type":"education","lineage":["https://openalex.org/I100887729"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"R. Manoj Kumar","raw_affiliation_strings":["Department of ECE, Andhra University College of Engineering(A), Andhra University, Visakhapatnam, Andhra Pradesh 530003, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Andhra University College of Engineering(A), Andhra University, Visakhapatnam, Andhra Pradesh 530003, India","institution_ids":["https://openalex.org/I100887729"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001176952","display_name":"P. V. Sridevi","orcid":"https://orcid.org/0000-0001-5998-0232"},"institutions":[{"id":"https://openalex.org/I100887729","display_name":"Andhra University","ror":"https://ror.org/049skhf47","country_code":"IN","type":"education","lineage":["https://openalex.org/I100887729"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. V. Sridevi","raw_affiliation_strings":["Department of ECE, Andhra University College of Engineering(A), Andhra University, Visakhapatnam, Andhra Pradesh 530003, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Andhra University College of Engineering(A), Andhra University, Visakhapatnam, Andhra Pradesh 530003, India","institution_ids":["https://openalex.org/I100887729"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5101823321"],"corresponding_institution_ids":["https://openalex.org/I100887729"],"apc_list":null,"apc_paid":null,"fwci":0.6242,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.68773284,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"30","issue":"08","first_page":"2150142","last_page":"2150142"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8572694063186646},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7819806933403015},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.657042384147644},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6028178334236145},{"id":"https://openalex.org/keywords/standby-power","display_name":"Standby power","score":0.5890752077102661},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49988603591918945},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4941406548023224},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.4640798568725586},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4551905691623688},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.4400857090950012},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.4361388683319092},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4332120716571808},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.4282096028327942},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.42636194825172424},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3210863173007965}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8572694063186646},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7819806933403015},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.657042384147644},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6028178334236145},{"id":"https://openalex.org/C7140552","wikidata":"https://www.wikidata.org/wiki/Q1366402","display_name":"Standby power","level":3,"score":0.5890752077102661},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49988603591918945},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4941406548023224},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4640798568725586},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4551905691623688},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.4400857090950012},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.4361388683319092},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4332120716571808},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.4282096028327942},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.42636194825172424},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3210863173007965},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126621501425","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126621501425","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1989243598","https://openalex.org/W2004965314","https://openalex.org/W2073772724","https://openalex.org/W2095913060","https://openalex.org/W2099087448","https://openalex.org/W2105175332","https://openalex.org/W2106339466","https://openalex.org/W2151529344","https://openalex.org/W2164330002","https://openalex.org/W2326541585","https://openalex.org/W2617377387","https://openalex.org/W2764168195","https://openalex.org/W2789254542","https://openalex.org/W2790878208","https://openalex.org/W2806948360","https://openalex.org/W2911288356","https://openalex.org/W2977558241"],"related_works":["https://openalex.org/W2039755656","https://openalex.org/W1949737515","https://openalex.org/W4253620068","https://openalex.org/W2042352336","https://openalex.org/W2027009856","https://openalex.org/W2144417859","https://openalex.org/W2147835582","https://openalex.org/W4240087758","https://openalex.org/W3024792827","https://openalex.org/W2800107826"],"abstract_inverted_index":{"The":[0,40,76],"technology":[1],"is":[2,64,74,207],"shrinking":[3],"in":[4,37,57,79,124,132,153,243,246],"recent":[5],"days":[6],"which":[7],"leads":[8],"to":[9,13,20,42,83,175],"growing":[10],"concerns":[11],"related":[12],"various":[14],"design":[15,81,234],"metrics.":[16],"Leakage":[17],"power":[18,170],"tends":[19],"grow":[21],"with":[22],"the":[23,29,46,51,67,70,95,99,116,135,157,192,233],"array":[24,97],"size":[25],"as":[26,50],"most":[27],"of":[28,120,129,134],"Static":[30],"Random":[31],"Access":[32],"Memory":[33],"(SRAM)":[34],"cells":[35,190,224],"operate":[36],"standby":[38],"mode.":[39],"data":[41],"be":[43,84,92],"written":[44],"into":[45],"SRAM":[47,63,80,96,110,189,223],"become":[48],"difficult":[49],"supply":[52,200,230],"voltage":[53,122],"decreases.":[54],"So,":[55],"stability":[56],"write":[58,72,144,148,154],"mode":[59,155],"requires":[60],"enhancement.":[61],"As":[62],"used":[65],"for":[66,94,197],"on-chip":[68],"computations,":[69],"faster":[71,143],"operation":[73,145],"required.":[75],"half-select":[77,158],"issue":[78,159],"needs":[82],"eliminated":[85],"so":[86],"that":[87],"bit":[88],"interleaving":[89],"architecture":[90],"can":[91],"employed":[93],"enabling":[98],"protection":[100],"from":[101],"soft":[102],"errors.":[103],"A":[104],"new":[105],"Proposed":[106],"10":[107],"Transistor":[108,181,188,215,222],"Bit-Interleaved":[109],"cell":[111],"has":[112,167],"been":[113,237],"designed":[114],"addressing":[115],"above":[117],"concerns.":[118],"Employment":[119],"high-threshold":[121],"devices":[123],"read":[125],"path":[126],"and":[127,146,182,216],"absence":[128],"NMOS":[130],"device":[131],"one":[133],"inverters":[136],"reduces":[137],"leakage":[138,169],"power.":[139],"Cut-off":[140],"switch":[141],"enables":[142],"enhanced":[147],"stability.":[149],"Cross":[150],"point":[151],"selection":[152],"eliminates":[156],"observed":[160],"by":[161,239],"carrying":[162],"1000":[163],"Monte-Carlo":[164],"simulations.":[165],"It":[166],"lower":[168,208],"while":[171],"holding":[172],"0":[173],"compared":[174],"8":[176,180,210,214],"Transistor,":[177,211],"Fully":[178,212],"Differential":[179,213],"Write":[183,202,217],"Assist":[184,218],"Low":[185,219],"Power":[186,204,220],"11":[187,221],"at":[191,225,228],"worst":[193],"fast-fast":[194],"process":[195],"corner":[196,227],"0.9":[198],"V":[199],"voltage.":[201,231],"1":[203],"Delay":[205],"Product":[206],"than":[209],"slow-slow":[226],"0.9V":[229],"All":[232],"metrics":[235],"have":[236],"evaluated":[238],"performing":[240],"post-layout":[241],"simulation":[242],"Cadence":[244],"Virtuoso":[245],"45-nm":[247],"technology.":[248]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}