{"id":"https://openalex.org/W3034141746","doi":"https://doi.org/10.1142/s0218126621500420","title":"Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio","display_name":"Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio","publication_year":2020,"publication_date":"2020-06-03","ids":{"openalex":"https://openalex.org/W3034141746","doi":"https://doi.org/10.1142/s0218126621500420","mag":"3034141746"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126621500420","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126621500420","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089926026","display_name":"Islam Ahmed","orcid":"https://orcid.org/0009-0009-0223-5149"},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Islam Ahmed","raw_affiliation_strings":["IC Verification Solutions, Mentor Graphics, a Siemens Business, Cairo 11361, Egypt"],"affiliations":[{"raw_affiliation_string":"IC Verification Solutions, Mentor Graphics, a Siemens Business, Cairo 11361, Egypt","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012834813","display_name":"Ahmed N. Mohieldin","orcid":"https://orcid.org/0000-0001-7500-4514"},"institutions":[{"id":"https://openalex.org/I145487455","display_name":"Cairo University","ror":"https://ror.org/03q21mh05","country_code":"EG","type":"education","lineage":["https://openalex.org/I145487455"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Ahmed Nader Mohieldin","raw_affiliation_strings":["Electronics and Communications Engineering Department, Cairo University, Giza 12613, Egypt"],"affiliations":[{"raw_affiliation_string":"Electronics and Communications Engineering Department, Cairo University, Giza 12613, Egypt","institution_ids":["https://openalex.org/I145487455"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063929219","display_name":"Hassan Mostafa","orcid":"https://orcid.org/0000-0003-0043-5007"},"institutions":[{"id":"https://openalex.org/I4210150948","display_name":"Zewail City of Science and Technology","ror":"https://ror.org/04w5f4y88","country_code":"EG","type":"education","lineage":["https://openalex.org/I4210150948"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Hassan Mostafa","raw_affiliation_strings":["University of Science and Technology, Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt"],"affiliations":[{"raw_affiliation_string":"University of Science and Technology, Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt","institution_ids":["https://openalex.org/I4210150948"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5063929219"],"corresponding_institution_ids":["https://openalex.org/I4210150948"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.07055749,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"30","issue":"03","first_page":"2150042","last_page":"2150042"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9240050315856934},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7510707378387451},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7020602822303772},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6362718939781189},{"id":"https://openalex.org/keywords/initialization","display_name":"Initialization","score":0.5531967282295227},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.49753764271736145},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.48502129316329956},{"id":"https://openalex.org/keywords/software-defined-radio","display_name":"Software-defined radio","score":0.4814526438713074},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.46967750787734985},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43441349267959595},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10756334662437439}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9240050315856934},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7510707378387451},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7020602822303772},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6362718939781189},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.5531967282295227},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.49753764271736145},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.48502129316329956},{"id":"https://openalex.org/C171115542","wikidata":"https://www.wikidata.org/wiki/Q1331892","display_name":"Software-defined radio","level":2,"score":0.4814526438713074},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.46967750787734985},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43441349267959595},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10756334662437439},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126621500420","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126621500420","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1497207433","https://openalex.org/W1969875970","https://openalex.org/W1980377171","https://openalex.org/W2104491791","https://openalex.org/W2132243305","https://openalex.org/W2158265605","https://openalex.org/W2585821329","https://openalex.org/W2621963703","https://openalex.org/W2806977884","https://openalex.org/W2890501436","https://openalex.org/W2890506436","https://openalex.org/W3144225254"],"related_works":["https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2797161794","https://openalex.org/W2096938998","https://openalex.org/W1760305469","https://openalex.org/W2340647897","https://openalex.org/W2808484818","https://openalex.org/W1574948540","https://openalex.org/W275424163"],"abstract_inverted_index":{"Dynamic":[0],"Partial":[1],"Reconfiguration":[2],"(DPR)":[3],"on":[4,75,82,167],"Field":[5],"Programmable":[6],"Gate":[7],"Arrays":[8],"(FPGAs)":[9],"allows":[10,29],"reconfiguration":[11,95,105],"of":[12,14,22,52,63,89,99,116,134,140,175],"some":[13],"the":[15,20,23,30,61,64,70,76,90,94,100,104,110,117,127,132,135,138,173,180],"logic":[16,24],"at":[17],"runtime":[18],"while":[19],"rest":[21],"keeps":[25],"operating.":[26],"This":[27,150],"feature":[28],"designers":[31],"to":[32,50,126,129,156,171],"build":[33],"complex":[34],"systems":[35,120],"such":[36,55],"as":[37,56],"Software-Defined":[38],"Radio":[39],"(SDR)":[40],"in":[41,179],"a":[42,83,122,168],"reasonable":[43],"area.":[44],"New":[45],"issues":[46],"can":[47],"arise":[48],"due":[49,125],"usage":[51],"DPR":[53],"technique":[54],"guaranteeing":[57],"proper":[58],"connections":[59],"for":[60,79,147,161],"ports":[62],"Reconfigurable":[65,72],"Modules":[66],"(RMs)":[67],"which":[68],"share":[69],"same":[71],"Region":[73],"(RR)":[74],"FPGA,":[77],"waiting":[78],"running":[80],"computations":[81],"module":[84,102],"before":[85],"reconfiguring":[86],"it,":[87],"isolation":[88],"reconfigurable":[91,101,119],"modules":[92],"during":[93],"process,":[96],"and":[97,137],"initialization":[98],"after":[103],"process":[106],"is":[107,121],"done.":[108],"Also,":[109],"Clock":[111],"Domain":[112],"Crossing":[113],"(CDC)":[114],"verification":[115,159],"dynamically":[118],"complicated":[123],"task":[124],"need":[128],"verify":[130],"all":[131],"modes":[133],"designs,":[136],"lack":[139],"Computer":[141],"Aided":[142],"Design":[143],"(CAD)":[144],"tools":[145],"support":[146],"DRS":[148],"designs.":[149],"paper":[151],"summarizes":[152],"our":[153],"previous":[154],"work":[155],"address":[157],"these":[158,177],"challenges":[160],"DPR.":[162],"The":[163],"approaches":[164,178],"are":[165],"demonstrated":[166],"SDR":[169],"system":[170],"show":[172],"effectiveness":[174],"applying":[176],"design":[181],"cycle.":[182]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
