{"id":"https://openalex.org/W2963583521","doi":"https://doi.org/10.1142/s021812662050098x","title":"<i>In-Situ</i> Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA","display_name":"<i>In-Situ</i> Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA","publication_year":2019,"publication_date":"2019-07-18","ids":{"openalex":"https://openalex.org/W2963583521","doi":"https://doi.org/10.1142/s021812662050098x","mag":"2963583521"},"language":"en","primary_location":{"id":"doi:10.1142/s021812662050098x","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s021812662050098x","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Minh Tung Dam","orcid":null},"institutions":[{"id":"https://openalex.org/I146824383","display_name":"Hallym University","ror":"https://ror.org/03sbhge02","country_code":"KR","type":"education","lineage":["https://openalex.org/I146824383"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Minh Tung Dam","raw_affiliation_strings":["E-SoC Lab, Department of Computer Science, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","Smart Computing Lab, Department of Computer Engineering, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"E-SoC Lab, Department of Computer Science, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","institution_ids":["https://openalex.org/I146824383"]},{"raw_affiliation_string":"Smart Computing Lab, Department of Computer Engineering, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","institution_ids":["https://openalex.org/I146824383"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Van Toan Nguyen","orcid":null},"institutions":[{"id":"https://openalex.org/I146824383","display_name":"Hallym University","ror":"https://ror.org/03sbhge02","country_code":"KR","type":"education","lineage":["https://openalex.org/I146824383"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Van Toan Nguyen","raw_affiliation_strings":["E-SoC Lab, Department of Computer Science, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","Smart Computing Lab, Department of Computer Engineering, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"E-SoC Lab, Department of Computer Science, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","institution_ids":["https://openalex.org/I146824383"]},{"raw_affiliation_string":"Smart Computing Lab, Department of Computer Engineering, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","institution_ids":["https://openalex.org/I146824383"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006775135","display_name":"Jeong\u2010Gun Lee","orcid":"https://orcid.org/0000-0001-6218-4560"},"institutions":[{"id":"https://openalex.org/I146824383","display_name":"Hallym University","ror":"https://ror.org/03sbhge02","country_code":"KR","type":"education","lineage":["https://openalex.org/I146824383"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Jeong-Gun Lee","raw_affiliation_strings":["E-SoC Lab, Department of Computer Science, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","Smart Computing Lab, Department of Computer Engineering, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"E-SoC Lab, Department of Computer Science, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","institution_ids":["https://openalex.org/I146824383"]},{"raw_affiliation_string":"Smart Computing Lab, Department of Computer Engineering, Hallym University, Chuncheon-si, Gangwon-do 24252, South Korea","institution_ids":["https://openalex.org/I146824383"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5006775135"],"corresponding_institution_ids":["https://openalex.org/I146824383"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06188462,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"29","issue":"06","first_page":"2050098","last_page":"2050098"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7241924405097961},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5981423258781433},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.5003433227539062},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.48609280586242676},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4651200771331787},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.46285122632980347},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4437463879585266},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.4417659044265747},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.43358373641967773},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4301976263523102},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.41570383310317993},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39477914571762085},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3477759063243866},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3439018428325653},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3383990526199341},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3258824944496155},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.26054245233535767},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.2332102358341217},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2124907672405243},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17114505171775818},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1686343550682068}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7241924405097961},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5981423258781433},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.5003433227539062},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.48609280586242676},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4651200771331787},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.46285122632980347},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4437463879585266},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.4417659044265747},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.43358373641967773},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4301976263523102},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.41570383310317993},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39477914571762085},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3477759063243866},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3439018428325653},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3383990526199341},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3258824944496155},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.26054245233535767},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.2332102358341217},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2124907672405243},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17114505171775818},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1686343550682068},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s021812662050098x","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s021812662050098x","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6600000262260437,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G4111361416","display_name":null,"funder_award_id":"2018R1D1A1B07043399","funder_id":"https://openalex.org/F4320320671","funder_display_name":"National Research Foundation"}],"funders":[{"id":"https://openalex.org/F4320320671","display_name":"National Research Foundation","ror":"https://ror.org/05s0g1g46"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1830929998","https://openalex.org/W1973985871","https://openalex.org/W1978172953","https://openalex.org/W2045656654","https://openalex.org/W2094981849","https://openalex.org/W2129314919","https://openalex.org/W2141412618","https://openalex.org/W2166667302","https://openalex.org/W2170058139","https://openalex.org/W2178304595","https://openalex.org/W2289333215","https://openalex.org/W2397888180","https://openalex.org/W2539987182","https://openalex.org/W2762216355","https://openalex.org/W4236432903"],"related_works":["https://openalex.org/W2116514610","https://openalex.org/W2003180247","https://openalex.org/W2144282137","https://openalex.org/W2891365107","https://openalex.org/W2032549010","https://openalex.org/W2391115906","https://openalex.org/W2169934076","https://openalex.org/W2138768308","https://openalex.org/W2098440959","https://openalex.org/W1999924508"],"abstract_inverted_index":{"In":[0,109],"this":[1,110],"paper,":[2],"a":[3,16,35,67,75,86,112,119,163,175,183],"timing":[4,29,150,160,239],"error":[5],"predictor":[6],"(TEP)":[7],"for":[8,39,84,132],"adaptive":[9],"frequency":[10,55,63,135,217],"scaling":[11,56],"(AFS)":[12],"is":[13,32,126,152,172,194],"proposed":[14,127,167,210],"on":[15,182],"field-programmable":[17],"gate":[18],"array":[19],"(FPGA).":[20],"The":[21,188,204],"use":[22],"of":[23,61,92,162,191],"TEP-based":[24,169,211],"AFS":[25,170,212],"can":[26,95],"minimize":[27],"large":[28],"margin":[30,161],"which":[31,117,148],"added":[33],"to":[34,101,128,156,174,228],"clock":[36,69,138,216,221],"cycle":[37,139],"time":[38],"tolerating":[40],"process,":[41],"voltage,":[42],"and":[43,98,180,201,223],"temperature":[44],"(PVT)":[45],"variations.":[46],"On":[47],"an":[48,124,145],"FPGA,":[49,125],"in":[50,66,123],"general,":[51],"the":[52,59,81,89,93,107,130,134,159,192,209,215,232,238],"typical":[53],"dynamic":[54,62],"has":[57,74],"used":[58],"feature":[60],"synthesis":[64],"(DFS)":[65],"digital":[68],"manager":[70],"(DCM).":[71],"However,":[72],"it":[73,99],"long":[76],"locking":[77],"time.":[78],"Moreover,":[79],"during":[80],"DCM":[82,94,131],"reconfiguration":[83],"generating":[85],"new":[87],"frequency,":[88],"lock":[90],"signal":[91],"be":[96],"lost":[97],"leads":[100],"possible":[102],"glitches":[103],"or":[104],"spikes":[105],"at":[106],"output.":[108],"work,":[111],"variable-length":[113],"ring":[114],"oscillator":[115],"(VLRO),":[116],"employs":[118],"high-speed":[120],"carry":[121],"chain":[122],"replace":[129],"changing":[133],"within":[136,219],"one":[137],"without":[140],"introducing":[141],"any":[142],"glitches.":[143],"Furthermore,":[144],"in-situ":[146,168],"TEP,":[147],"detects":[149],"errors,":[151],"combined":[153],"with":[154],"VLRO":[155],"further":[157],"reduce":[158],"target":[164],"system.":[165],"Our":[166],"scheme":[171],"applied":[173],"[Formula:":[176,229],"see":[177,230],"text]-bit":[178],"multiplier":[179],"implemented":[181],"Spartan-6":[184],"FPGA":[185],"device":[186],"(XFC6SLX45).":[187],"functional":[189],"correctness":[190],"TEP":[193],"verified":[195],"under":[196],"various":[197],"DC":[198],"supply":[199],"voltages":[200],"operating":[202,234],"frequencies.":[203],"experimental":[205],"results":[206],"show":[207],"that":[208],"system":[213],"switches":[214],"correctly":[218],"two":[220],"cycles":[222],"improves":[224],"circuit":[225],"performance":[226],"up":[227],"text]":[231],"nominal":[233],"condition":[235],"by":[236],"minimizing":[237],"margin.":[240]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}