{"id":"https://openalex.org/W2883259301","doi":"https://doi.org/10.1142/s0218126619501081","title":"A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application","display_name":"A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application","publication_year":2018,"publication_date":"2018-07-22","ids":{"openalex":"https://openalex.org/W2883259301","doi":"https://doi.org/10.1142/s0218126619501081","mag":"2883259301"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126619501081","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126619501081","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051418913","display_name":"Pritam Bhattacharjee","orcid":"https://orcid.org/0000-0002-1968-1622"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Pritam Bhattacharjee","raw_affiliation_strings":["Integrated Circuit and System (i-CAS) Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Arunachal Pradesh, Yupia, Papum Pare 791112, Arunachal Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Integrated Circuit and System (i-CAS) Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Arunachal Pradesh, Yupia, Papum Pare 791112, Arunachal Pradesh, India","institution_ids":["https://openalex.org/I57496824"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009067589","display_name":"Alak Majumder","orcid":"https://orcid.org/0000-0003-4775-8591"},"institutions":[{"id":"https://openalex.org/I57496824","display_name":"National Institute of Technology Arunachal Pradesh","ror":"https://ror.org/020cr8c43","country_code":"IN","type":"education","lineage":["https://openalex.org/I57496824"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Alak Majumder","raw_affiliation_strings":["Integrated Circuit and System (i-CAS) Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Arunachal Pradesh, Yupia, Papum Pare 791112, Arunachal Pradesh, India"],"affiliations":[{"raw_affiliation_string":"Integrated Circuit and System (i-CAS) Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Arunachal Pradesh, Yupia, Papum Pare 791112, Arunachal Pradesh, India","institution_ids":["https://openalex.org/I57496824"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5051418913"],"corresponding_institution_ids":["https://openalex.org/I57496824"],"apc_list":null,"apc_paid":null,"fwci":0.7725,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.73636262,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"28","issue":"07","first_page":"1950108","last_page":"1950108"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.8318411111831665},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6966637372970581},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"Transmission gate","score":0.6634694337844849},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6300734281539917},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6107996702194214},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5211334824562073},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5023248195648193},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5020792484283447},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4673217833042145},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.46267789602279663},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45503780245780945},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4235611855983734},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.41526561975479126},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.29694944620132446},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2879416346549988},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.225176602602005},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12574145197868347},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08014979958534241}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.8318411111831665},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6966637372970581},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.6634694337844849},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6300734281539917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6107996702194214},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5211334824562073},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5023248195648193},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5020792484283447},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4673217833042145},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.46267789602279663},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45503780245780945},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4235611855983734},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.41526561975479126},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.29694944620132446},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2879416346549988},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.225176602602005},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12574145197868347},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08014979958534241},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126619501081","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126619501081","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7900000214576721,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320325255","display_name":"Ministry of Electronics and Information technology","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W646410877","https://openalex.org/W1518236483","https://openalex.org/W1543643719","https://openalex.org/W1776668917","https://openalex.org/W1941494887","https://openalex.org/W1971306575","https://openalex.org/W2011882362","https://openalex.org/W2031970782","https://openalex.org/W2043128052","https://openalex.org/W2047694997","https://openalex.org/W2065016886","https://openalex.org/W2076608835","https://openalex.org/W2076941902","https://openalex.org/W2081968143","https://openalex.org/W2114132980","https://openalex.org/W2131619025","https://openalex.org/W2150306869","https://openalex.org/W2326715752","https://openalex.org/W2515437249","https://openalex.org/W2559648591","https://openalex.org/W2581647284","https://openalex.org/W2593332647","https://openalex.org/W2783069494","https://openalex.org/W2785560680"],"related_works":["https://openalex.org/W2797823235","https://openalex.org/W1808420522","https://openalex.org/W2360732944","https://openalex.org/W2120898945","https://openalex.org/W4406795382","https://openalex.org/W2611474147","https://openalex.org/W2535130387","https://openalex.org/W3111333564","https://openalex.org/W4313404246","https://openalex.org/W2371966460"],"abstract_inverted_index":{"Advancement":[0],"in":[1,44,136,151,159,211,225],"technology":[2],"towards":[3],"mobile":[4],"computing":[5],"and":[6,40,48,94,120,124,172,196,202,219],"communication":[7],"demands":[8],"longer":[9],"battery":[10],"life,":[11],"which":[12,32,60],"mandates":[13],"the":[14,35,69,73,118,129,165,226],"low":[15],"power":[16,47,122,137,178],"design":[17],"methodologies.":[18],"In":[19],"this":[20,54,145],"paper,":[21],"we":[22,76],"have":[23,77,108],"presented":[24],"a":[25,57,100,152,177],"novel":[26],"low-power":[27,160],"8T":[28],"flip-flop":[29,131,148],"(FF)":[30],"architecture,":[31],"has":[33],"outsmarted":[34],"existing":[36],"well-known":[37],"dynamic,":[38],"semi-dynamic":[39],"explicit":[41],"pulsed":[42],"flip-flops":[43],"terms":[45],"of":[46,53,72,85,102,144,180,217,228],"delay.":[49],"The":[50,142,190,214],"major":[51],"ingredient":[52],"architecture":[55],"is":[56,61,149],"voltage":[58],"keeper,":[59],"incorporated":[62],"to":[63,111,115,128,132,207],"achieve":[64,133],"reliable":[65],"logic":[66,97],"switching":[67],"at":[68,184],"propagating":[70],"nodes":[71],"design.":[74,163],"However,":[75],"also":[78],"come":[79],"up":[80],"with":[81,156,176,205],"two":[82],"new":[83],"approaches":[84],"gated":[86,147,191,218],"clock":[87,188],"generation":[88],"based":[89],"on":[90],"transmission":[91],"gate":[92],"(TG)":[93],"pass":[95],"transistor":[96],"(PTL)":[98],"as":[99],"modification":[101],"LECTOR-based":[103],"gating.":[104],"These":[105],"gating":[106],"logics":[107],"proved":[109],"themselves":[110],"be":[112],"competent":[113],"enough":[114],"reduce":[116],"both":[117],"static":[119],"dynamic":[121],"dissipations":[123],"hence":[125],"are":[126,167,223],"employed":[127],"proposed":[130,146,221],"further":[134],"reduction":[135],"than":[138],"its":[139,157,208],"nongated":[140,209,220],"correspondent.":[141],"performance":[143,215],"tested":[150],"finite":[153],"state":[154],"machine":[155],"application":[158],"serial":[161],"adder":[162],"All":[164],"simulations":[166],"carried":[168],"out":[169],"using":[170],"65-nm":[171,212],"90-nm":[173],"CMOS":[174,230],"technologies":[175],"supply":[179],"1.1[Formula:":[181],"see":[182,186],"text]V":[183],"6.6[Formula:":[185],"text]GHz":[187],"frequency.":[189],"FF":[192],"saves":[193],"52.12%,":[194],"6.36%":[195],"28.18%":[197],"average":[198],"power-using":[199],"LECTOR,":[200],"TG":[201],"PTLs,":[203],"respectively,":[204],"respect":[206],"counterpart":[210],"technology.":[213],"metrics":[216],"designs":[222],"affirmed":[224],"environment":[227],"commercialized":[229],"foundry.":[231]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
