{"id":"https://openalex.org/W2806866037","doi":"https://doi.org/10.1142/s0218126619500610","title":"Automated Generation of Synchronous Formal Models from SystemC Descriptions","display_name":"Automated Generation of Synchronous Formal Models from SystemC Descriptions","publication_year":2018,"publication_date":"2018-05-27","ids":{"openalex":"https://openalex.org/W2806866037","doi":"https://doi.org/10.1142/s0218126619500610","mag":"2806866037"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126619500610","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126619500610","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050188272","display_name":"Hamoudi Kalla","orcid":"https://orcid.org/0000-0003-0257-7367"},"institutions":[{"id":"https://openalex.org/I162489102","display_name":"University of Batna 1","ror":"https://ror.org/04hrbe508","country_code":"DZ","type":"education","lineage":["https://openalex.org/I162489102"]}],"countries":["DZ"],"is_corresponding":true,"raw_author_name":"Hamoudi Kalla","raw_affiliation_strings":["LaSTIC Laboratory, Department of Computer Science, University of Batna 2, 53, Route de Constantine. Fesdis, Batna 05078, Algeria"],"affiliations":[{"raw_affiliation_string":"LaSTIC Laboratory, Department of Computer Science, University of Batna 2, 53, Route de Constantine. Fesdis, Batna 05078, Algeria","institution_ids":["https://openalex.org/I162489102"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049070037","display_name":"David Berner","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Berner","raw_affiliation_strings":["INRIA Rennes, Campus de Beaulieu, 50, Route de Malagnou, 1208 Geneva, Switzerland"],"affiliations":[{"raw_affiliation_string":"INRIA Rennes, Campus de Beaulieu, 50, Route de Malagnou, 1208 Geneva, Switzerland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010968465","display_name":"Jean-Pierre Talpin","orcid":"https://orcid.org/0000-0002-0556-4265"},"institutions":[{"id":"https://openalex.org/I1326498283","display_name":"Institut national de recherche en informatique et en automatique","ror":"https://ror.org/02kvxyf05","country_code":"FR","type":"funder","lineage":["https://openalex.org/I1326498283"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean-Pierre Talpin","raw_affiliation_strings":["INRIA Rennes, Campus de Beaulieu, 263 Avenue General Leclerc, 35042 Rennes, France"],"affiliations":[{"raw_affiliation_string":"INRIA Rennes, Campus de Beaulieu, 263 Avenue General Leclerc, 35042 Rennes, France","institution_ids":["https://openalex.org/I1326498283"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5050188272"],"corresponding_institution_ids":["https://openalex.org/I162489102"],"apc_list":null,"apc_paid":null,"fwci":0.263,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.5001744,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"28","issue":"04","first_page":"1950061","last_page":"1950061"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.96857750415802},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8659287095069885},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.6554096937179565},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6545668244361877},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.6462326049804688},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.5649052262306213},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.47305670380592346},{"id":"https://openalex.org/keywords/formal-semantics","display_name":"Formal semantics (linguistics)","score":0.4461532235145569},{"id":"https://openalex.org/keywords/formal-specification","display_name":"Formal specification","score":0.4392582178115845},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.42842769622802734},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4153469204902649},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.33744335174560547},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2843135595321655}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.96857750415802},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8659287095069885},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.6554096937179565},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6545668244361877},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.6462326049804688},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.5649052262306213},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.47305670380592346},{"id":"https://openalex.org/C146499914","wikidata":"https://www.wikidata.org/wiki/Q5469969","display_name":"Formal semantics (linguistics)","level":2,"score":0.4461532235145569},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.4392582178115845},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.42842769622802734},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4153469204902649},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.33744335174560547},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2843135595321655},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126619500610","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126619500610","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1982205631","https://openalex.org/W2031381504","https://openalex.org/W2046555386","https://openalex.org/W2055295051","https://openalex.org/W2072922398","https://openalex.org/W2076600865","https://openalex.org/W2169132374","https://openalex.org/W2531335688","https://openalex.org/W2767982805"],"related_works":["https://openalex.org/W4233602124","https://openalex.org/W2156965212","https://openalex.org/W2790192245","https://openalex.org/W4232281993","https://openalex.org/W3146089259","https://openalex.org/W1984090905","https://openalex.org/W4247397443","https://openalex.org/W2035296141","https://openalex.org/W2131133849","https://openalex.org/W2133071611"],"abstract_inverted_index":{"SystemC":[0,45,54,122,138],"is":[1,13,124,130,144],"one":[2],"of":[3,27,35,74,83,104,109,115],"the":[4,60,67,72,107,110,113,116,119,127,133,140,149],"most":[5],"popular":[6],"electronic":[7],"system-level":[8],"design":[9,46],"language":[10,63],"and":[11,39,70,85,87,95,112,126,146],"it":[12],"embraced":[14],"by":[15],"a":[16,24,32,44,80],"growing":[17],"community":[18],"that":[19,100],"seeks":[20],"to":[21,23],"move":[22],"higher":[25],"level":[26],"abstraction.":[28],"It":[29],"lacks":[30],"however":[31],"standard":[33],"way":[34],"integrating":[36],"formal":[37,40,61,75],"methods":[38],"verification":[41,76,89],"techniques":[42],"into":[43,59,148],"flow.":[47],"In":[48,118,132],"this":[49],"paper,":[50],"we":[51,101],"show":[52],"how":[53],"descriptions":[55],"are":[56],"automatically":[57],"transformed":[58],"synchronous":[62],"Signal,":[64],"while":[65],"conserving":[66],"original":[68],"structure":[69,111],"enabling":[71],"application":[73],"techniques.":[77],"Signal":[78,142,152],"provides":[79],"simple":[81],"semantics":[82],"concurrency":[84],"time,":[86],"allows":[88],"with":[90],"an":[91],"existing":[92],"theorem":[93],"prover":[94],"model":[96,123],"checker.":[97],"The":[98],"approach":[99],"propose":[102],"consists":[103],"two":[105],"steps:":[106],"extraction":[108],"transformation":[114],"behavior.":[117],"first":[120],"step,":[121,135],"analyzed":[125],"structural":[128],"information":[129],"extracted.":[131],"second":[134],"for":[136],"each":[137],"module,":[139],"corresponding":[141],"behavior":[143],"generated":[145],"filled":[147],"already":[150],"prepared":[151],"structure.":[153]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-03-17T09:09:15.849793","created_date":"2025-10-10T00:00:00"}
