{"id":"https://openalex.org/W2795551195","doi":"https://doi.org/10.1142/s0218126619500117","title":"A SAT-Based Methodology for Effective Clock Gating for Power Minimization","display_name":"A SAT-Based Methodology for Effective Clock Gating for Power Minimization","publication_year":2018,"publication_date":"2018-04-06","ids":{"openalex":"https://openalex.org/W2795551195","doi":"https://doi.org/10.1142/s0218126619500117","mag":"2795551195"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126619500117","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126619500117","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018650380","display_name":"Khushbu Chandrakar","orcid":null},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Khushbu Chandrakar","raw_affiliation_strings":["Department of Computer Science and Engineering, National Institute of Technology, Durgapur, WB 713209, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Institute of Technology, Durgapur, WB 713209, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103190077","display_name":"Suchismita Roy","orcid":"https://orcid.org/0000-0002-7313-1453"},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Suchismita Roy","raw_affiliation_strings":["Department of Computer Science and Engineering, National Institute of Technology, Durgapur, WB 713209, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Institute of Technology, Durgapur, WB 713209, India","institution_ids":["https://openalex.org/I155837530"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I155837530"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.04684435,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"28","issue":"01","first_page":"1950011","last_page":"1950011"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9238619804382324},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.68874591588974},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6701174378395081},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.613764762878418},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5283440351486206},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5139457583427429},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5070202350616455},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.48890557885169983},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4864828288555145},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.48184406757354736},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.46899083256721497},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.43286392092704773},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4265028238296509},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39078593254089355},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3237353563308716},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.2565925121307373},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1887529194355011},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1236257553100586}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9238619804382324},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.68874591588974},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6701174378395081},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.613764762878418},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5283440351486206},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5139457583427429},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5070202350616455},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.48890557885169983},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4864828288555145},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.48184406757354736},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.46899083256721497},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.43286392092704773},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4265028238296509},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39078593254089355},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3237353563308716},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.2565925121307373},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1887529194355011},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1236257553100586},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126619500117","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126619500117","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W633814207","https://openalex.org/W1985602827","https://openalex.org/W2062763371","https://openalex.org/W2078854425","https://openalex.org/W2111046960","https://openalex.org/W2123953188","https://openalex.org/W2128876681","https://openalex.org/W2136047350","https://openalex.org/W2152938140","https://openalex.org/W2203862213","https://openalex.org/W2493328864"],"related_works":["https://openalex.org/W2337711143","https://openalex.org/W2071461855","https://openalex.org/W1995174288","https://openalex.org/W2069695849","https://openalex.org/W2619074915","https://openalex.org/W2787335253","https://openalex.org/W2156372158","https://openalex.org/W2383792991","https://openalex.org/W2795551195","https://openalex.org/W2373321430"],"abstract_inverted_index":{"A":[0,24,154],"possible":[1],"solution":[2],"to":[3,13,66,86],"handle":[4],"the":[5,15,20,49,63,69,88,96,111,119,124,140,146,151,167,174,178,184],"rising":[6],"complexity":[7],"of":[8,17,27,44,68,91,98,110,150,169,177],"modern":[9],"Systems-on-Chip":[10],"(SoCs)":[11],"is":[12,134,159],"raise":[14],"level":[16],"abstraction":[18,36],"for":[19],"design":[21],"and":[22,29,75,131,145],"optimization.":[23],"better":[25],"optimization":[26,41],"performance":[28],"power":[30,58,89,148,170,185],"can":[31],"be":[32],"achieved":[33],"at":[34],"higher":[35],"levels":[37],"by":[38,60,94,117,172],"applying":[39],"suitable":[40],"techniques.":[42],"Insertion":[43],"clock":[45,64,103,112,120,125,152,179],"gating":[46,118,123],"logic":[47,141],"into":[48],"generated":[50],"Register-Transfer":[51],"Level":[52],"(RTL)":[53],"would":[54],"facilitate":[55],"lowering":[56],"dynamic":[57],"consumption":[59,90,149,171,186],"switching":[61],"off":[62,116],"signal":[65,126],"portions":[67],"circuit":[70,142],"not":[71],"currently":[72],"in":[73,161],"use":[74],"thereby":[76],"reducing":[77,95,173],"unnecessary":[78],"toggling.":[79],"In":[80],"this":[81,162],"work,":[82],"we":[83],"have":[84,105],"tried":[85],"minimize":[87],"synchronous":[92],"circuits":[93],"number":[97],"activity":[99,175],"string":[100],"patterns.":[101],"Activity-driven":[102],"trees":[104],"been":[106],"used":[107],"wherein":[108],"sections":[109],"tree":[113,180],"are":[114],"turned":[115],"signals.":[121],"Since":[122],"implies":[127],"additional":[128],"control":[129],"signals":[130],"gates,":[132],"there":[133],"always":[135],"a":[136],"trade-off":[137],"existing":[138],"between":[139],"area":[143],"overhead":[144],"total":[147],"tree.":[153],"pseudo-Boolean":[155],"satisfiability":[156],"(PB-SAT)-based":[157],"approach":[158],"proposed":[160],"work":[163],"which":[164,181],"focuses":[165],"on":[166],"reduction":[168],"pattern":[176],"will":[182],"reduce":[183],"with":[187],"appropriate":[188],"module-binding":[189],"solutions.":[190]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}