{"id":"https://openalex.org/W2739622812","doi":"https://doi.org/10.1142/s0218126618500524","title":"Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)","display_name":"Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)","publication_year":2017,"publication_date":"2017-07-31","ids":{"openalex":"https://openalex.org/W2739622812","doi":"https://doi.org/10.1142/s0218126618500524","mag":"2739622812"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126618500524","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126618500524","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038665000","display_name":"P Sasipriya","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"P. Sasipriya","raw_affiliation_strings":["School of Electronics Engineering, VIT University, Chennai 600127, Tamilnadu, India"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, VIT University, Chennai 600127, Tamilnadu, India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030426808","display_name":"V. S. Kanchana Bhaaskaran","orcid":"https://orcid.org/0000-0002-3819-1952"},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"V. S. Kanchana Bhaaskaran","raw_affiliation_strings":["School of Electronics Engineering, VIT University, Chennai 600127, Tamilnadu, India"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, VIT University, Chennai 600127, Tamilnadu, India","institution_ids":["https://openalex.org/I876193797"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038665000"],"corresponding_institution_ids":["https://openalex.org/I876193797"],"apc_list":null,"apc_paid":null,"fwci":0.2867,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.58916914,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"27","issue":"04","first_page":"1850052","last_page":"1850052"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.8497523069381714},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.643399715423584},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.631159245967865},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6054505109786987},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6017526388168335},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.593442440032959},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5700753927230835},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5523043870925903},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5298874974250793},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4742419123649597},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46160948276519775},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.4213646352291107},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3682304322719574},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33340340852737427},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2505285143852234},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.24409878253936768},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14987564086914062},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.057586103677749634}],"concepts":[{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.8497523069381714},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.643399715423584},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.631159245967865},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6054505109786987},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6017526388168335},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.593442440032959},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5700753927230835},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5523043870925903},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5298874974250793},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4742419123649597},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46160948276519775},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.4213646352291107},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3682304322719574},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33340340852737427},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2505285143852234},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.24409878253936768},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14987564086914062},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.057586103677749634}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126618500524","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126618500524","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1544558177","https://openalex.org/W1994446366","https://openalex.org/W2022448319","https://openalex.org/W2026990972","https://openalex.org/W2028364018","https://openalex.org/W2036300206","https://openalex.org/W2041255146","https://openalex.org/W2041425962","https://openalex.org/W2045383911","https://openalex.org/W2059463062","https://openalex.org/W2085952730","https://openalex.org/W2088828547","https://openalex.org/W2098750459","https://openalex.org/W2099889623","https://openalex.org/W2105946429","https://openalex.org/W2106659921","https://openalex.org/W2116676845","https://openalex.org/W2119512278","https://openalex.org/W2122984966","https://openalex.org/W2123607016","https://openalex.org/W2129886330","https://openalex.org/W2138360154","https://openalex.org/W2255043861","https://openalex.org/W2553550675"],"related_works":["https://openalex.org/W2580743037","https://openalex.org/W1889611132","https://openalex.org/W2894573466","https://openalex.org/W2965791759","https://openalex.org/W2108907112","https://openalex.org/W2126241630","https://openalex.org/W3080459857","https://openalex.org/W2770128534","https://openalex.org/W4255074571","https://openalex.org/W2178256824"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,27,33,49,55,81,116,148,182,192,201,210],"quasi-adiabatic":[4],"logic":[5,18,24,51,66,83,158,163,169,184],"for":[6,59,100,187],"low":[7],"power":[8,76,177],"powered":[9],"by":[10,69,190],"two":[11,20,70],"phase":[12,21],"sinusoidal":[13],"clock":[14,72],"signal.":[15],"The":[16,64,78,141,179,197,215],"proposed":[17,50,82],"called":[19],"adiabatic":[22,105,151,162],"dynamic":[23],"(2PADL)":[25],"realizes":[26],"advantages":[28],"of":[29,35,61,80,128,181,212],"energy":[30,96,123,156,204],"efficiency":[31,124],"through":[32,87],"use":[34],"gate":[36],"overdrive":[37],"and":[38,48,119,130,165,174,206],"reduced":[39],"switching":[40],"power.":[41],"It":[42],"has":[43],"a":[44,126,132],"single":[45],"rail":[46],"output":[47],"does":[52],"not":[53],"require":[54],"complementary":[56,71],"input":[57],"signals":[58,73],"any":[60],"its":[62,122,176],"variables.":[63],"2PADL":[65,113,136,173],"is":[67,84,144,185,203],"operated":[68],"acting":[74],"as":[75,91],"supply.":[77],"validation":[79],"carried":[85,218],"out":[86,219],"practical":[88],"circuits":[89,94],"such":[90],"(i)":[92],"sequential":[93],"using":[95,112,135,147,220,226],"recovery":[97,157],"technique":[98],"suitable":[99],"memory":[101],"circuits,":[102],"(ii)":[103],"an":[104],"carry":[106],"look":[107],"ahead":[108],"adder":[109,143],"(CLA)":[110],"designed":[111],"to":[114,120,170,209],"study":[115],"speed":[117],"performance":[118,180],"prove":[121],"across":[125],"range":[127],"frequencies":[129,189],"(iii)":[131],"multiplier":[133],"circuit":[134],"compared":[137],"against":[138,172],"CMOS":[139,161,168],"counterpart.":[140],"CLA":[142,195],"also":[145],"implemented":[146],"other":[149],"static":[150,155,167],"logics,":[152],"namely,":[153],"quasi":[154],"(QSERL),":[159],"clocked":[160],"(CCAL)":[164],"conventional":[166],"compare":[171],"validate":[175],"advantages.":[178],"CCAL":[183],"tested":[186],"higher":[188],"implementing":[191],"widely":[193],"presented":[194],"circuit.":[196],"result":[198],"proves":[199],"that":[200],"design":[202],"efficient":[205],"operates":[207],"up":[208],"frequency":[211],"600":[213],"MHz.":[214],"simulation":[216],"was":[217],"industry":[221],"standard":[222],"Cadence\u00ae":[223],"Virtuoso":[224],"tool":[225],"180[Formula:":[227],"see":[228],"text]nm":[229],"technology":[230],"library":[231],"files.":[232]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}