{"id":"https://openalex.org/W2608015824","doi":"https://doi.org/10.1142/s0218126617501869","title":"New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies","display_name":"New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies","publication_year":2017,"publication_date":"2017-04-28","ids":{"openalex":"https://openalex.org/W2608015824","doi":"https://doi.org/10.1142/s0218126617501869","mag":"2608015824"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126617501869","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126617501869","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022476734","display_name":"Neeta Pandey","orcid":"https://orcid.org/0000-0003-2911-7061"},"institutions":[{"id":"https://openalex.org/I863896202","display_name":"Delhi Technological University","ror":"https://ror.org/01ztcvt22","country_code":"IN","type":"education","lineage":["https://openalex.org/I863896202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Neeta Pandey","raw_affiliation_strings":["Department of ECE, Delhi Technological University, (Formerly Delhi College of Engineering), Delhi 110042, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Delhi Technological University, (Formerly Delhi College of Engineering), Delhi 110042, India","institution_ids":["https://openalex.org/I863896202"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019332578","display_name":"Bharat Choudhary","orcid":"https://orcid.org/0000-0002-7311-1815"},"institutions":[{"id":"https://openalex.org/I863896202","display_name":"Delhi Technological University","ror":"https://ror.org/01ztcvt22","country_code":"IN","type":"education","lineage":["https://openalex.org/I863896202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bharat Choudhary","raw_affiliation_strings":["Department of ECE, Delhi Technological University, (Formerly Delhi College of Engineering), Delhi 110042, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, Delhi Technological University, (Formerly Delhi College of Engineering), Delhi 110042, India","institution_ids":["https://openalex.org/I863896202"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082620922","display_name":"Kirti Gupta","orcid":"https://orcid.org/0000-0003-0565-0654"},"institutions":[{"id":"https://openalex.org/I887998513","display_name":"Bharati Vidyapeeth Deemed University","ror":"https://ror.org/0052mmx10","country_code":"IN","type":"education","lineage":["https://openalex.org/I887998513"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kirti Gupta","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Bharati Vidyapeeth\u2019s College of Engineering, Delhi 110063, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Bharati Vidyapeeth\u2019s College of Engineering, Delhi 110063, India","institution_ids":["https://openalex.org/I887998513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051965447","display_name":"Ankit Mittal","orcid":"https://orcid.org/0000-0001-8761-2269"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ankit Mittal","raw_affiliation_strings":["Department of EEE/E&I, Birla Institute of Technology Pilani University, (K. K. Birla Goa Campus), Goa 403726, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of EEE/E&I, Birla Institute of Technology Pilani University, (K. K. Birla Goa Campus), Goa 403726, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1462,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.49127333,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"26","issue":"12","first_page":"1750186","last_page":"1750186"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.8746565580368042},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6476829051971436},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6268784403800964},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5627702474594116},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5564711093902588},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5416406393051147},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5244957804679871},{"id":"https://openalex.org/keywords/buffer","display_name":"Buffer (optical fiber)","score":0.49426889419555664},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47698551416397095},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.46895331144332886},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.45284971594810486},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4396817982196808},{"id":"https://openalex.org/keywords/sleep","display_name":"Sleep (system call)","score":0.4114856719970703},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4107101261615753},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3111163377761841},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.297172874212265},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14379695057868958},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13787364959716797},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12166321277618408},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11073604226112366},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08966401219367981},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.0701269805431366}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.8746565580368042},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6476829051971436},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6268784403800964},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5627702474594116},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5564711093902588},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5416406393051147},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5244957804679871},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.49426889419555664},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47698551416397095},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.46895331144332886},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.45284971594810486},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4396817982196808},{"id":"https://openalex.org/C2775841894","wikidata":"https://www.wikidata.org/wiki/Q4683692","display_name":"Sleep (system call)","level":2,"score":0.4114856719970703},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4107101261615753},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3111163377761841},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.297172874212265},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14379695057868958},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13787364959716797},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12166321277618408},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11073604226112366},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08966401219367981},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0701269805431366},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126617501869","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126617501869","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8500000238418579,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W194061475","https://openalex.org/W2099984297","https://openalex.org/W2135286216","https://openalex.org/W2284115081","https://openalex.org/W3142526730"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W1943174035","https://openalex.org/W2096437374","https://openalex.org/W3211084114","https://openalex.org/W2035475131","https://openalex.org/W2769457990","https://openalex.org/W4281385583","https://openalex.org/W1941788997","https://openalex.org/W2116129710","https://openalex.org/W2548285782"],"abstract_inverted_index":{"This":[0,28],"paper":[1],"describes":[2],"new":[3,56],"sleep-based":[4,75],"positive":[5],"feedback":[6],"source-coupled":[7],"logic":[8],"(PFSCL)":[9],"tri-state":[10,14,77],"inverter/buffer":[11],"topologies.":[12,57],"The":[13,47,58,97],"behavior":[15],"is":[16,29,66,103],"obtained":[17],"by":[18,31],"disconnecting":[19],"the":[20,36,44,50,63,89,100],"circuit":[21,79],"from":[22],"both":[23],"power":[24],"supply":[25],"and":[26,60,86,92,107],"ground.":[27],"achieved":[30],"placing":[32],"additional":[33],"transistors,":[34],"driving":[35],"load":[37],"transistor":[38],"to":[39],"cut":[40],"off":[41],"or":[42],"disabling":[43],"current":[45],"source.":[46],"combination":[48],"of":[49,62,84,99],"three":[51],"methods":[52],"results":[53],"in":[54,88],"six":[55],"functionality":[59],"performance":[61],"proposed":[64,101],"topologies":[65,102],"studied":[67],"through":[68,105],"SPICE":[69],"simulations.":[70],"A":[71],"comparison":[72],"with":[73],"available":[74],"PFSCL":[76],"buffer":[78],"shows":[80],"a":[81],"maximum":[82],"reduction":[83],"11%":[85],"60%":[87],"propagation":[90],"delay":[91],"output":[93],"enable":[94],"time,":[95],"respectively.":[96],"usefulness":[98],"illustrated":[104],"bus":[106],"D":[108],"latch":[109],"implementation.":[110]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}