{"id":"https://openalex.org/W2605659784","doi":"https://doi.org/10.1142/s0218126617501699","title":"Fully Differential Class-AB OTA with Improved CMRR","display_name":"Fully Differential Class-AB OTA with Improved CMRR","publication_year":2017,"publication_date":"2017-04-11","ids":{"openalex":"https://openalex.org/W2605659784","doi":"https://doi.org/10.1142/s0218126617501699","mag":"2605659784"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126617501699","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126617501699","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030782483","display_name":"Francesco Centurelli","orcid":"https://orcid.org/0000-0003-3880-2546"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Francesco Centurelli","raw_affiliation_strings":["Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070430111","display_name":"Pietro Monsurr\u00f2","orcid":"https://orcid.org/0000-0002-3821-6566"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pietro Monsurr\u00f2","raw_affiliation_strings":["Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104858381","display_name":"Gaetano Parisi","orcid":null},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gaetano Parisi","raw_affiliation_strings":["Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081472410","display_name":"Pasquale Tommasino","orcid":"https://orcid.org/0000-0002-3744-2158"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pasquale Tommasino","raw_affiliation_strings":["Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068452963","display_name":"Alessandro Trifiletti","orcid":"https://orcid.org/0000-0001-6231-4273"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Trifiletti","raw_affiliation_strings":["Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria dell\u2019Informazione, Elettronica e Telecomunicazioni, Universit\u00e0 di Roma La Sapienza, Via Eudossiana, 18 Roma 00184, Italy","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5030782483"],"corresponding_institution_ids":["https://openalex.org/I861853513"],"apc_list":null,"apc_paid":null,"fwci":0.1301,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.45987673,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"26","issue":"11","first_page":"1750169","last_page":"1750169"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/common-mode-signal","display_name":"Common-mode signal","score":0.7738935947418213},{"id":"https://openalex.org/keywords/common-mode-rejection-ratio","display_name":"Common-mode rejection ratio","score":0.7563546895980835},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6336694955825806},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5847070813179016},{"id":"https://openalex.org/keywords/differential","display_name":"Differential (mechanical device)","score":0.5800649523735046},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.5698788166046143},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.5579133033752441},{"id":"https://openalex.org/keywords/differential-amplifier","display_name":"Differential amplifier","score":0.5006356239318848},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49869275093078613},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48386919498443604},{"id":"https://openalex.org/keywords/current-mirror","display_name":"Current mirror","score":0.47421005368232727},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.47399938106536865},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.431146502494812},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.37480971217155457},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2710234522819519},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.25257664918899536},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22263166308403015},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20374777913093567},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12534227967262268},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11763158440589905},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.10987326502799988}],"concepts":[{"id":"https://openalex.org/C189714311","wikidata":"https://www.wikidata.org/wiki/Q1530371","display_name":"Common-mode signal","level":4,"score":0.7738935947418213},{"id":"https://openalex.org/C102309569","wikidata":"https://www.wikidata.org/wiki/Q1244941","display_name":"Common-mode rejection ratio","level":5,"score":0.7563546895980835},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6336694955825806},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5847070813179016},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.5800649523735046},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.5698788166046143},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.5579133033752441},{"id":"https://openalex.org/C11722477","wikidata":"https://www.wikidata.org/wiki/Q1056298","display_name":"Differential amplifier","level":4,"score":0.5006356239318848},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49869275093078613},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48386919498443604},{"id":"https://openalex.org/C173966970","wikidata":"https://www.wikidata.org/wiki/Q786012","display_name":"Current mirror","level":4,"score":0.47421005368232727},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.47399938106536865},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.431146502494812},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.37480971217155457},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2710234522819519},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.25257664918899536},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22263166308403015},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20374777913093567},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12534227967262268},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11763158440589905},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.10987326502799988},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1142/s0218126617501699","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126617501699","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/984919","is_oa":false,"landing_page_url":"http://www.worldscinet.com/jcsc/jcsc.shtml","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1578814374","https://openalex.org/W1967807522","https://openalex.org/W1998284495","https://openalex.org/W2012963133","https://openalex.org/W2127142182","https://openalex.org/W2154597885","https://openalex.org/W2177594704"],"related_works":["https://openalex.org/W2020854411","https://openalex.org/W1500249877","https://openalex.org/W66547677","https://openalex.org/W1748565700","https://openalex.org/W2165510722","https://openalex.org/W4206451047","https://openalex.org/W2113246691","https://openalex.org/W3093504667","https://openalex.org/W1877685702","https://openalex.org/W3036943836"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2,19],"a":[3,16,34,58,75],"fully":[4],"differential":[5],"class-AB":[6],"current":[7],"mirror":[8],"OTA":[9],"that":[10,18],"improves":[11],"the":[12,40,45,48,72,79],"common-mode":[13,26,49,62],"behavior":[14],"of":[15,47,61,64],"topology":[17],"very":[20],"good":[21],"differential-mode":[22,73],"performance":[23],"but":[24],"poor":[25],"rejection":[27],"ratio":[28],"(CMRR).":[29],"The":[30],"proposed":[31,80],"solution":[32],"requires":[33],"low-current":[35],"auxiliary":[36],"circuit":[37],"driven":[38],"by":[39],"input":[41,50],"signal,":[42],"to":[43],"compensate":[44],"effect":[46],"component.":[51],"Simulations":[52],"in":[53],"40-nm":[54],"CMOS":[55],"technology":[56],"show":[57],"net":[59],"reduction":[60],"gain":[63],"more":[65],"than":[66],"90[Formula:":[67],"see":[68],"text]dB":[69],"without":[70],"affecting":[71],"behavior;":[74],"sample-and-hold":[76],"amplifier":[77,81],"exploiting":[78],"has":[82],"also":[83],"been":[84],"simulated.":[85]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}