{"id":"https://openalex.org/W2501300322","doi":"https://doi.org/10.1142/s021812661650153x","title":"Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique","display_name":"Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique","publication_year":2016,"publication_date":"2016-07-20","ids":{"openalex":"https://openalex.org/W2501300322","doi":"https://doi.org/10.1142/s021812661650153x","mag":"2501300322"},"language":"en","primary_location":{"id":"doi:10.1142/s021812661650153x","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s021812661650153x","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056138326","display_name":"Vinay Kumar","orcid":"https://orcid.org/0000-0002-3759-9091"},"institutions":[{"id":"https://openalex.org/I9523339","display_name":"National Institute of Technology Meghalaya","ror":"https://ror.org/020vd6n84","country_code":"IN","type":"education","lineage":["https://openalex.org/I9523339"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vinay Kumar","raw_affiliation_strings":["Department of ECE, NIT Meghalaya, Shillong, Meghalaya 793003, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, NIT Meghalaya, Shillong, Meghalaya 793003, India","institution_ids":["https://openalex.org/I9523339"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069928017","display_name":"Anup Dandapat","orcid":"https://orcid.org/0000-0002-0997-1220"},"institutions":[{"id":"https://openalex.org/I9523339","display_name":"National Institute of Technology Meghalaya","ror":"https://ror.org/020vd6n84","country_code":"IN","type":"education","lineage":["https://openalex.org/I9523339"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Anup Dandapat","raw_affiliation_strings":["Department of ECE, NIT Meghalaya, Shillong, Meghalaya 793003, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, NIT Meghalaya, Shillong, Meghalaya 793003, India","institution_ids":["https://openalex.org/I9523339"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5069928017"],"corresponding_institution_ids":["https://openalex.org/I9523339"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06625853,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":"12","first_page":"1650153","last_page":"1650153"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.8912527561187744},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6582430601119995},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5698224902153015},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49669843912124634},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4602483808994293},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4421149492263794},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.41090911626815796},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.364641010761261},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.357564240694046},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3276470899581909},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15798333287239075},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08705958724021912}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.8912527561187744},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6582430601119995},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5698224902153015},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49669843912124634},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4602483808994293},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4421149492263794},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.41090911626815796},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.364641010761261},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.357564240694046},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3276470899581909},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15798333287239075},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08705958724021912},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s021812661650153x","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s021812661650153x","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W25571951","https://openalex.org/W1978909743","https://openalex.org/W2012661299","https://openalex.org/W2024223745","https://openalex.org/W2036887642","https://openalex.org/W2053619330","https://openalex.org/W2067776562","https://openalex.org/W2089303278","https://openalex.org/W2092333098","https://openalex.org/W2114781590","https://openalex.org/W2155097858","https://openalex.org/W2157341826","https://openalex.org/W2158748448","https://openalex.org/W2159318488","https://openalex.org/W2161011111","https://openalex.org/W3141112769"],"related_works":["https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W2163776294","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W4248668797","https://openalex.org/W2111485030","https://openalex.org/W4390345338","https://openalex.org/W96064250","https://openalex.org/W2169337913"],"abstract_inverted_index":{"Conventional":[0],"combinational":[1,24,35,50,69,92,185],"circuits":[2,9,36,142,188],"are":[3,189,218],"generally":[4],"acyclic":[5],"(feed-forward)":[6],"but":[7,107],"these":[8],"can":[10],"have":[11],"feedbacks":[12,32,116],"(cycles)":[13],"which":[14,158,177],"will":[15],"give":[16],"more":[17,115],"minimized":[18],"expressions":[19,66,131,153],"as":[20,97],"compared":[21,219],"to":[22,63,79,147,173],"conventional":[23,34,222],"circuits.":[25,51,70,89,223],"Deliberate":[26],"incorporation":[27],"of":[28,43,48,60,67,76,126,154,216],"such":[29],"cycles":[30,127],"or":[31,84,114],"in":[33,39,41,45,54,74,81,149,193],"eventually":[37],"results":[38],"reduction":[40,53,80,145,163],"number":[42,59,75],"literals":[44],"the":[46,49,58,65,68,72,88,98,109,133,162,169,221],"expression":[47],"The":[52,135,187],"literal":[55,150],"counts":[56,83,151],"decreases":[57],"gates":[61,77],"required":[62],"implement":[64,174],"Hence,":[71],"decrease":[73],"leads":[78],"transistor":[82],"layout":[85,214],"area":[86,215],"for":[87,124,132,152],"A":[90],"cyclic":[91,184],"circuit":[93,99],"(CCC)":[94],"is":[95,137,159,171],"defined":[96],"whose":[100],"output":[101],"depends":[102],"on":[103,139,203],"present":[104],"inputs":[105],"only,":[106],"at":[108],"same":[110],"time":[111],"contains":[112],"one":[113],"(cycles).":[117],"This":[118],"paper":[119],"presents":[120],"a":[121,144],"simplified":[122],"methodology":[123,136,170],"introduction":[125],"(feedbacks)":[128],"and":[129,143,213],"finding":[130],"CCC.":[134],"applied":[138,172],"LGSynth93":[140],"benchmark":[141],"up":[146],"28%":[148],"CCC":[155,217],"was":[156],"found":[157],"higher":[160],"than":[161],"achieved":[164],"by":[165],"other":[166],"methodologies.":[167],"Further":[168],"binary":[175],"comparator":[176],"has":[178],"got":[179],"three":[180],"multiple":[181],"outputs":[182],"using":[183,197],"technique.":[186],"verified":[190],"through":[191],"simulation":[192,204],"cadence":[194],"virtuoso":[195],"tools":[196],"45[Formula:":[198],"see":[199],"text]nm":[200],"technology.":[201],"Based":[202],"results,":[205],"performance":[206],"parameters":[207],"like":[208],"power":[209],"consumption,":[210],"propagation":[211],"delay":[212],"with":[220]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
