{"id":"https://openalex.org/W1826123170","doi":"https://doi.org/10.1142/s0218126616500092","title":"A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms","display_name":"A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms","publication_year":2015,"publication_date":"2015-10-09","ids":{"openalex":"https://openalex.org/W1826123170","doi":"https://doi.org/10.1142/s0218126616500092","mag":"1826123170"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126616500092","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126616500092","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037093590","display_name":"Daniel Mealha Cabrita","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Daniel Mealha Cabrita","raw_affiliation_strings":["Ministerio Publico do Estado do Parana (MP-PR) Curitiba, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ministerio Publico do Estado do Parana (MP-PR) Curitiba, Brazil","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018546513","display_name":"Carlos R. Erig Lima","orcid":"https://orcid.org/0000-0002-4026-4444"},"institutions":[{"id":"https://openalex.org/I1283613182","display_name":"Universidade Tecnol\u00f3gica Federal do Paran\u00e1","ror":"https://ror.org/002v2kq79","country_code":"BR","type":"education","lineage":["https://openalex.org/I1283613182"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Carlos Raimundo Erig Lima","raw_affiliation_strings":["Federal University of Technology \u2013 Parana (UTFPR) Curitiba, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Federal University of Technology \u2013 Parana (UTFPR) Curitiba, Brazil","institution_ids":["https://openalex.org/I1283613182"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02697433,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"25","issue":"02","first_page":"1650009","last_page":"1650009"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10494","display_name":"Plant Virus Research Studies","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/1110","display_name":"Plant Science"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},"topics":[{"id":"https://openalex.org/T10494","display_name":"Plant Virus Research Studies","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/1110","display_name":"Plant Science"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10878","display_name":"CRISPR and Genetic Engineering","score":0.9901000261306763,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9868000149726868,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.8420798778533936},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.761127233505249},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7455347776412964},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7112621068954468},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.701791524887085},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5741247534751892},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5697572827339172},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5508980751037598},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5164937973022461},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5030412077903748},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.4633306562900543},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4422873854637146},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.42461609840393066},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33283984661102295},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.20676574110984802},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1711898148059845},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11830109357833862},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.07522675395011902}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.8420798778533936},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.761127233505249},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7455347776412964},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7112621068954468},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.701791524887085},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5741247534751892},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5697572827339172},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5508980751037598},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5164937973022461},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5030412077903748},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.4633306562900543},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4422873854637146},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.42461609840393066},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33283984661102295},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20676574110984802},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1711898148059845},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11830109357833862},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07522675395011902},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126616500092","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126616500092","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W102100901","https://openalex.org/W1542869478","https://openalex.org/W1572929635","https://openalex.org/W1576818901","https://openalex.org/W1901232807","https://openalex.org/W1994861165","https://openalex.org/W2018094844","https://openalex.org/W2033390283","https://openalex.org/W2039140951","https://openalex.org/W2051242802","https://openalex.org/W2054921155","https://openalex.org/W2090389046","https://openalex.org/W2107490398","https://openalex.org/W2110487025","https://openalex.org/W2119974776","https://openalex.org/W2148348448","https://openalex.org/W2326114135","https://openalex.org/W2329329248","https://openalex.org/W2914145474","https://openalex.org/W4231510479","https://openalex.org/W4233183865"],"related_works":["https://openalex.org/W4248668797","https://openalex.org/W2153257783","https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W2111485030","https://openalex.org/W2085176210","https://openalex.org/W2169337913","https://openalex.org/W3114476551"],"abstract_inverted_index":{"Current":[0],"works":[1,46,72,160],"on":[2,95,131],"generation":[3],"of":[4,24,37,39,62,116,119,164],"combinational":[5,25],"logic":[6],"circuits":[7,83],"(CLC)":[8],"using":[9,15],"evolutionary":[10],"algorithms":[11],"(EA)":[12],"propose":[13,110],"solutions":[14,80],"field-programmable":[16],"gate":[17],"array":[18],"(FPGA)":[19],"to":[20,33,48,75,81,85,135,157],"accelerate":[21],"the":[22,35,44,50,54,57,96,103,132],"process":[23],"circuit":[26,58,88,104,146],"simulation,":[27],"a":[28,67],"step":[29],"needed":[30],"in":[31,71,162],"order":[32],"evaluate":[34],"level":[36],"correctness":[38],"each":[40],"individual":[41],"circuit.":[42],"However,":[43],"current":[45],"fail":[47,74],"separate":[49],"two":[51],"distinct":[52],"problems:":[53],"EA":[55,134],"and":[56,84,127,148,166],"simulator.":[59],"The":[60,122],"insistence":[61],"treating":[63],"both":[64,161],"problem":[65,106],"as":[66],"single":[68],"one":[69],"results":[70,143,150],"that":[73,152],"address":[76,102],"either":[77],"properly,":[78],"restricting":[79],"simple":[82],"topologically":[86],"restrictive":[87],"simulators,":[89],"while":[90],"providing":[91],"very":[92],"limited":[93],"data":[94],"results.":[97],"In":[98],"this":[99],"work,":[100],"we":[101,109],"simulator":[105],"exclusively,":[107],"where":[108],"an":[111],"architecture":[112,124,154],"for":[113,144],"fast":[114],"simulation":[115],"n-LUT":[117],"CLC":[118],"arbitrary":[120],"topology.":[121],"proposed":[123],"is":[125,155],"modular":[126],"makes":[128],"no":[129],"assumptions":[130],"specific":[133],"be":[136],"used":[137],"with.":[138],"We":[139],"provide":[140],"detailed":[141],"performance":[142,165],"varying":[145],"dimensions,":[147],"those":[149],"show":[151],"our":[153],"able":[156],"surpass":[158],"other":[159],"terms":[163],"topological":[167],"flexibility.":[168]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
