{"id":"https://openalex.org/W1786720068","doi":"https://doi.org/10.1142/s0218126616400223","title":"An Early Stage Design Flow for Switching Noise Attenuation","display_name":"An Early Stage Design Flow for Switching Noise Attenuation","publication_year":2015,"publication_date":"2015-10-19","ids":{"openalex":"https://openalex.org/W1786720068","doi":"https://doi.org/10.1142/s0218126616400223","mag":"1786720068"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126616400223","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126616400223","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054188213","display_name":"Steffen Zeidler","orcid":null},"institutions":[{"id":"https://openalex.org/I4210159354","display_name":"Institut f\u00fcr Solartechnologien (Germany)","ror":"https://ror.org/0529ecj14","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210159354"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Steffen Zeidler","raw_affiliation_strings":["IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany","institution_ids":["https://openalex.org/I4210159354"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034733719","display_name":"Xin Fan","orcid":"https://orcid.org/0000-0001-6954-5074"},"institutions":[{"id":"https://openalex.org/I4210159354","display_name":"Institut f\u00fcr Solartechnologien (Germany)","ror":"https://ror.org/0529ecj14","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210159354"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Xin Fan","raw_affiliation_strings":["IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany","institution_ids":["https://openalex.org/I4210159354"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041968870","display_name":"Oliver Schrape","orcid":"https://orcid.org/0000-0002-3513-3239"},"institutions":[{"id":"https://openalex.org/I4210159354","display_name":"Institut f\u00fcr Solartechnologien (Germany)","ror":"https://ror.org/0529ecj14","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210159354"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Oliver Schrape","raw_affiliation_strings":["IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany","institution_ids":["https://openalex.org/I4210159354"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004959402","display_name":"Milo\u0161 Krsti\u0107","orcid":"https://orcid.org/0000-0003-0267-0203"},"institutions":[{"id":"https://openalex.org/I4210159354","display_name":"Institut f\u00fcr Solartechnologien (Germany)","ror":"https://ror.org/0529ecj14","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210159354"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Milo\u0161 Krsti\u0107","raw_affiliation_strings":["IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany","institution_ids":["https://openalex.org/I4210159354"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5054188213"],"corresponding_institution_ids":["https://openalex.org/I4210159354"],"apc_list":null,"apc_paid":null,"fwci":0.2008,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.57581398,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"25","issue":"03","first_page":"1640022","last_page":"1640022"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ground-bounce","display_name":"Ground bounce","score":0.7096897959709167},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7050971984863281},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6788558959960938},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5875363945960999},{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.5415106415748596},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48953279852867126},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4706774353981018},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4630809724330902},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.45270535349845886},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.44035011529922485},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4247239828109741},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.4102349579334259},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.316636860370636},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3052750825881958},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.294364333152771},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12747856974601746},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.12250277400016785}],"concepts":[{"id":"https://openalex.org/C179053373","wikidata":"https://www.wikidata.org/wiki/Q1547690","display_name":"Ground bounce","level":5,"score":0.7096897959709167},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7050971984863281},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6788558959960938},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5875363945960999},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.5415106415748596},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48953279852867126},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4706774353981018},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4630809724330902},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.45270535349845886},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.44035011529922485},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4247239828109741},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.4102349579334259},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.316636860370636},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3052750825881958},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.294364333152771},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12747856974601746},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.12250277400016785},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C166972891","wikidata":"https://www.wikidata.org/wiki/Q5527011","display_name":"Gate dielectric","level":4,"score":0.0},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126616400223","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126616400223","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320338388","display_name":"Eurostars","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1944814515","https://openalex.org/W1994898876","https://openalex.org/W2160658599","https://openalex.org/W2894705485","https://openalex.org/W4241311691"],"related_works":["https://openalex.org/W2250058922","https://openalex.org/W4386105410","https://openalex.org/W2050038301","https://openalex.org/W2182902404","https://openalex.org/W1963745701","https://openalex.org/W2246813539","https://openalex.org/W2128725285","https://openalex.org/W2147709302","https://openalex.org/W2072347033","https://openalex.org/W2351022998"],"abstract_inverted_index":{"In":[0,67,92],"the":[1,36,45,59,64,70,74,82,90,104,115],"design":[2,60,99,112,122,142],"of":[3,47,58,73,106,110],"highly":[4],"complex":[5],"integrated":[6],"circuits":[7],"(ICs),":[8],"switching":[9,37],"noise":[10,108,134],"is":[11],"a":[12,97,111],"raising":[13],"problem.":[14],"To":[15],"handle":[16],"this,":[17],"current":[18,25],"shaping":[19],"techniques":[20,34],"are":[21,52,77],"applied":[22],"to":[23,44],"reduce":[24],"peaks":[26],"causing":[27],"ground":[28],"bounce":[29],"and":[30],"voltage":[31],"drops.":[32],"Such":[33],"distribute":[35],"activity":[38],"by":[39],"adding":[40],"phases":[41,57,84],"and/or":[42],"jitter":[43],"clock":[46,83,125,138],"different":[48],"domains.":[49,91],"However,":[50],"they":[51],"usually":[53],"performed":[54],"at":[55,114],"later":[56,141],"process,":[61],"i.e.,":[62],"in":[63,140],"chip":[65],"layout.":[66],"this":[68,93],"phase,":[69],"timing":[71],"margins":[72],"logic":[75],"paths":[76],"typically":[78],"fixed,":[79],"which":[80,102,131],"limit":[81],"that":[85],"can":[86],"be":[87],"introduced":[88],"between":[89],"paper,":[94],"we":[95],"present":[96],"novel":[98],"preconditioning":[100],"flow,":[101],"addresses":[103],"optimization":[105],"power":[107],"characteristics":[109],"already":[113],"frontend":[116],"level.":[117],"This":[118],"allows":[119],"early":[120],"RTL-level":[121],"modifications,":[123],"e.g.,":[124],"inversion":[126],"or":[127,136],"pipeline":[128],"stage":[129],"insertion,":[130],"potentially":[132],"facilitate":[133],"mitigation":[135],"enhance":[137],"skewing":[139],"stages.":[143]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}