{"id":"https://openalex.org/W2240053671","doi":"https://doi.org/10.1142/s0218126615501303","title":"High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells","display_name":"High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells","publication_year":2015,"publication_date":"2015-07-29","ids":{"openalex":"https://openalex.org/W2240053671","doi":"https://doi.org/10.1142/s0218126615501303","mag":"2240053671"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126615501303","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615501303","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014244364","display_name":"Yavar Safaei Mehrabani","orcid":"https://orcid.org/0000-0003-1391-631X"},"institutions":[{"id":"https://openalex.org/I155419210","display_name":"Islamic Azad University, Science and Research Branch","ror":"https://ror.org/03187yj51","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433","https://openalex.org/I155419210"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Yavar Safaei Mehrabani","raw_affiliation_strings":["Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran","institution_ids":["https://openalex.org/I155419210"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001681499","display_name":"Mohammad Eshghi","orcid":"https://orcid.org/0000-0003-3878-6363"},"institutions":[{"id":"https://openalex.org/I48379061","display_name":"Shahid Beheshti University","ror":"https://ror.org/0091vmj44","country_code":"IR","type":"education","lineage":["https://openalex.org/I48379061"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohammad Eshghi","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran","institution_ids":["https://openalex.org/I48379061"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3215,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.66722722,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"24","issue":"09","first_page":"1550130","last_page":"1550130"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6929916739463806},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6761040687561035},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6587603688240051},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.6382499933242798},{"id":"https://openalex.org/keywords/nanoelectronics","display_name":"Nanoelectronics","score":0.6152901649475098},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5266625285148621},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4846847355365753},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.44403332471847534},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38926196098327637},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.38425374031066895},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33134937286376953},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.20793047547340393},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20427945256233215},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.18737241625785828},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18456819653511047},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.16872674226760864},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16511955857276917},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08266398310661316},{"id":"https://openalex.org/keywords/chemistry","display_name":"Chemistry","score":0.08041968941688538},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07521802186965942}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6929916739463806},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6761040687561035},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6587603688240051},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.6382499933242798},{"id":"https://openalex.org/C141400236","wikidata":"https://www.wikidata.org/wiki/Q1479544","display_name":"Nanoelectronics","level":2,"score":0.6152901649475098},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5266625285148621},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4846847355365753},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.44403332471847534},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38926196098327637},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38425374031066895},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33134937286376953},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.20793047547340393},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20427945256233215},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.18737241625785828},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18456819653511047},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.16872674226760864},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16511955857276917},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08266398310661316},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.08041968941688538},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07521802186965942},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126615501303","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615501303","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4399999976158142,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1970235797","https://openalex.org/W1972013943","https://openalex.org/W1979931298","https://openalex.org/W1983198901","https://openalex.org/W1985674454","https://openalex.org/W1992764350","https://openalex.org/W1993466043","https://openalex.org/W1994049178","https://openalex.org/W1995758143","https://openalex.org/W1999420559","https://openalex.org/W2012150093","https://openalex.org/W2018858346","https://openalex.org/W2032288511","https://openalex.org/W2036475592","https://openalex.org/W2047343930","https://openalex.org/W2075725718","https://openalex.org/W2093897975","https://openalex.org/W2096738483","https://openalex.org/W2097922215","https://openalex.org/W2103818395","https://openalex.org/W2110947114","https://openalex.org/W2113192550","https://openalex.org/W2120132584","https://openalex.org/W2135674775","https://openalex.org/W2137106200","https://openalex.org/W2146113745","https://openalex.org/W2147577254","https://openalex.org/W2158956219","https://openalex.org/W2159229333","https://openalex.org/W2165303371","https://openalex.org/W2169245181","https://openalex.org/W2170824658","https://openalex.org/W2172161464","https://openalex.org/W2963035981"],"related_works":["https://openalex.org/W3006681749","https://openalex.org/W2809889545","https://openalex.org/W1948588291","https://openalex.org/W3165307257","https://openalex.org/W3129152221","https://openalex.org/W2515312339","https://openalex.org/W2145098804","https://openalex.org/W2058461810","https://openalex.org/W4226211266","https://openalex.org/W2991151827"],"abstract_inverted_index":{"In":[0,15,26,56],"this":[1],"paper,":[2],"three":[3],"CNT-based":[4,102],"full":[5],"adder":[6],"designs,":[7],"called":[8,78],"Design1,":[9],"Design2":[10,79],"and":[11,20,33,80,101,105,118],"Design3,":[12],"are":[13,23,36,51,82,120],"proposed.":[14],"these":[16],"designs":[17,28],"12,":[18],"14":[19],"16":[21],"transistors":[22,70],"used,":[24],"respectively.":[25],"all":[27],"only":[29],"3-input":[30],"NAND,":[31],"Majority-not":[32],"NOR":[34],"functions":[35,173],"used.":[37],"First,":[38],"a":[39,61],"preliminary":[40],"structure":[41],"(Design1)":[42],"is":[43,64,87,133,152,161],"presented":[44,65],"using":[45,122,163],"12":[46],"transistors.":[47],"Then":[48],"its":[49,72],"weaknesses":[50],"tackled":[52],"in":[53,58,84],"two":[54,68,75],"steps.":[55],"fact,":[57],"each":[59],"step":[60],"new":[62,76],"design":[63],"by":[66],"adding":[67],"more":[69],"to":[71,112,135],"predecessor.":[73],"Therefore":[74],"structures":[77],"Design3":[81,86,97,144,172],"built":[83],"which":[85,151],"the":[88,94,130,136,141,146,155],"most":[89,156],"efficient":[90],"one.":[91],"To":[92],"study":[93],"performance":[95],"of":[96,143,149,154,159],"versus":[98],"other":[99,137],"silicon-based":[100],"32-nm":[103],"classical":[104],"state-of-the-art":[106],"cells,":[107],"comprehensive":[108],"simulations":[109],"with":[110],"regard":[111],"various":[113],"supplies,":[114],"loads,":[115],"operating":[116],"frequencies,":[117],"temperatures":[119],"performed":[121],"Synopsys":[123],"HSPICE":[124],"tool.":[125],"Simulation":[126],"results":[127],"confirm":[128],"that":[129,171],"proposed":[131],"cell":[132],"superior":[134],"cells.":[138],"At":[139],"last":[140],"robustness":[142],"against":[145,176],"diameter":[147],"mismatches":[148],"CNTs":[150],"one":[153],"important":[157],"concerns":[158],"nanoelectronics":[160],"studied":[162],"Monte":[164],"Carlo":[165],"transient":[166],"analysis.":[167],"This":[168],"simulation":[169],"reveals":[170],"very":[174],"well":[175],"manufacturing":[177],"process":[178],"variations.":[179]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}