{"id":"https://openalex.org/W1919667303","doi":"https://doi.org/10.1142/s0218126615501017","title":"High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations","display_name":"High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations","publication_year":2015,"publication_date":"2015-05-21","ids":{"openalex":"https://openalex.org/W1919667303","doi":"https://doi.org/10.1142/s0218126615501017","mag":"1919667303"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126615501017","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615501017","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014335296","display_name":"Raouf Senhadji-Navarro","orcid":"https://orcid.org/0000-0002-2838-9367"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Raouf Senhadji-Navaro","raw_affiliation_strings":["Computer Architecture and Technology Department, Higher Technical School of Computer Engineering, University of Seville, Avda. Reina Mercedes s/n, Seville 41012, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture and Technology Department, Higher Technical School of Computer Engineering, University of Seville, Avda. Reina Mercedes s/n, Seville 41012, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087818740","display_name":"Ignacio Garc\u00eda-Vargas","orcid":"https://orcid.org/0000-0001-8420-8770"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ignacio Garcia-Vargas","raw_affiliation_strings":["Computer Architecture and Technology Department, Higher Technical School of Computer Engineering, University of Seville, Avda. Reina Mercedes s/n, Seville 41012, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Architecture and Technology Department, Higher Technical School of Computer Engineering, University of Seville, Avda. Reina Mercedes s/n, Seville 41012, Spain","institution_ids":["https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I79238269"],"apc_list":null,"apc_paid":null,"fwci":0.677,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.73877462,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"24","issue":"07","first_page":"1550101","last_page":"1550101"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.9579640626907349},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8769171237945557},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.7177749872207642},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.690748929977417},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6114410758018494},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5638982057571411},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.5037881731987},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4466615915298462},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44347497820854187},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4206119179725647},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11416921019554138},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11093294620513916}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.9579640626907349},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8769171237945557},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.7177749872207642},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.690748929977417},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6114410758018494},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5638982057571411},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.5037881731987},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4466615915298462},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44347497820854187},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4206119179725647},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11416921019554138},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11093294620513916},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126615501017","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615501017","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1977850862","https://openalex.org/W1982157141","https://openalex.org/W2021407120","https://openalex.org/W2021918284"],"related_works":["https://openalex.org/W2039899645","https://openalex.org/W2371342700","https://openalex.org/W2327110311","https://openalex.org/W2363059241","https://openalex.org/W3215187042","https://openalex.org/W4233510838","https://openalex.org/W266342242","https://openalex.org/W2041812497","https://openalex.org/W2096209714","https://openalex.org/W2100439961"],"abstract_inverted_index":{"This":[0],"work":[1],"is":[2,60,74,88,108],"focused":[3],"on":[4],"the":[5,38,103],"problem":[6],"of":[7,16,37,51,57,84,94,106,112],"designing":[8],"efficient":[9],"reconfigurable":[10,17,27,43,96],"multiplexer":[11,28,44,86],"banks":[12,87],"for":[13],"RAM-based":[14],"implementations":[15],"state":[18,67,97],"machines.":[19],"We":[20],"propose":[21],"a":[22,91,95],"new":[23],"architecture":[24,40],"(called":[25,41],"combination-based":[26],"bank,":[29,45],"CRMUX)":[30],"that":[31,36,72,102,111],"use":[32],"multiplexers":[33],"simpler":[34],"than":[35,79,110],"state-of-the-art":[39],"variation-based":[42],"VRMUX).":[46],"The":[47,81,99],"performance":[48],"(in":[49],"terms":[50],"speed,":[52],"area":[53],"and":[54,76],"reconfiguration":[55,82,104],"cost)":[56],"both":[58,85],"architectures":[59],"compared.":[61],"Experimental":[62],"results":[63,100],"from":[64],"MCNC":[65],"finite":[66],"machine":[68],"(FSM)":[69],"benchmarks":[70],"show":[71,101],"CRMUX":[73,107],"faster":[75],"more":[77],"area-efficient":[78],"VRMUX.":[80],"cost":[83,105],"studied":[89],"using":[90],"behavioral":[92],"model":[93],"machine.":[98],"lower":[109],"VRMUX":[113],"in":[114],"most":[115],"cases.":[116]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}