{"id":"https://openalex.org/W2192675398","doi":"https://doi.org/10.1142/s0218126615500991","title":"Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays","display_name":"Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays","publication_year":2015,"publication_date":"2015-05-15","ids":{"openalex":"https://openalex.org/W2192675398","doi":"https://doi.org/10.1142/s0218126615500991","mag":"2192675398"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126615500991","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615500991","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060755096","display_name":"Jigang Wu","orcid":"https://orcid.org/0000-0002-6470-9794"},"institutions":[{"id":"https://openalex.org/I139024713","display_name":"Guangdong University of Technology","ror":"https://ror.org/04azbjn80","country_code":"CN","type":"education","lineage":["https://openalex.org/I139024713"]},{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"government","lineage":["https://openalex.org/I19820366"]},{"id":"https://openalex.org/I4210090176","display_name":"Institute of Computing Technology","ror":"https://ror.org/0090r4d87","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210090176"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jigang Wu","raw_affiliation_strings":["School of Computer Science and Technology, Guangdong University of Technology, Guangzhou 510006, China","State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Technology, Guangdong University of Technology, Guangzhou 510006, China","institution_ids":["https://openalex.org/I139024713"]},{"raw_affiliation_string":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China","institution_ids":["https://openalex.org/I4210090176","https://openalex.org/I19820366"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033922170","display_name":"Xiaogang Han","orcid":"https://orcid.org/0000-0002-4785-6506"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Xiaogang Han","raw_affiliation_strings":["School of Computer Engineering, Nanyang Technological University, Singapore 639798, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Engineering, Nanyang Technological University, Singapore 639798, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5060755096"],"corresponding_institution_ids":["https://openalex.org/I139024713","https://openalex.org/I19820366","https://openalex.org/I4210090176"],"apc_list":null,"apc_paid":null,"fwci":0.3385,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66923283,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"24","issue":"07","first_page":"1550099","last_page":"1550099"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.9025135040283203},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.8317371606826782},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8274209499359131},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5524210929870605},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5022778511047363},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4522061347961426},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.44181740283966064},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3906399607658386},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23325049877166748},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1754947304725647},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.05162322521209717}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.9025135040283203},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.8317371606826782},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8274209499359131},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5524210929870605},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5022778511047363},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4522061347961426},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.44181740283966064},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3906399607658386},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23325049877166748},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1754947304725647},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.05162322521209717},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126615500991","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615500991","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1590529339","https://openalex.org/W2004622965","https://openalex.org/W2044637290","https://openalex.org/W2049690883","https://openalex.org/W2121732188","https://openalex.org/W2146393011","https://openalex.org/W2149423787","https://openalex.org/W2162584664","https://openalex.org/W2165068028","https://openalex.org/W2171918708"],"related_works":["https://openalex.org/W2357657342","https://openalex.org/W2153432761","https://openalex.org/W1580144672","https://openalex.org/W2152623100","https://openalex.org/W2142042635","https://openalex.org/W4214878056","https://openalex.org/W4248634784","https://openalex.org/W2103296973","https://openalex.org/W1988127757","https://openalex.org/W2165091308"],"abstract_inverted_index":{"Reconfiguring":[0],"a":[1,13,26,35,57,94],"very":[2],"large":[3,22],"scale":[4],"integration":[5],"(VLSI)":[6],"array":[7,24,117],"with":[8,72,118],"faults":[9],"is":[10,79,91,108,126],"to":[11,46,60,86,111],"construct":[12],"maximum":[14],"logical":[15],"sub-array":[16],"(target":[17],"array)":[18],"without":[19,131],"faults.":[20,74],"A":[21],"target":[23],"implies":[25],"good":[27],"harvest":[28,41,67],"of":[29,39,50,65,133],"the":[30,40,48,51,62,66,69,83,88,105,122],"corresponding":[31,123],"reconfiguration":[32,52,95,124],"algorithm.":[33,53],"Thus,":[34],"tight":[36],"upper":[37,63,77,89,106],"bound":[38,64,78,90,92,107],"can":[42],"be":[43],"directly":[44],"used":[45],"evaluate":[47],"performance":[49],"This":[54],"paper":[55],"presents":[56],"new":[58],"approach":[59],"calculate":[61,87],"for":[68],"VLSI":[70],"arrays":[71],"clustered":[73,119],"The":[75],"latest":[76],"successfully":[80],"reduced":[81,109],"and":[82,121],"proposed":[84],"technique":[85],"into":[93],"algorithm":[96],"cited":[97],"in":[98],"this":[99],"paper.":[100],"Simulation":[101],"results":[102],"show":[103],"that":[104],"up":[110],"20%":[112],"on":[113],"256":[114,116],"\u00d7":[115],"faults,":[120],"process":[125],"significantly":[127],"accelerated":[128],"over":[129],"30%,":[130],"loss":[132],"harvest.":[134]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}