{"id":"https://openalex.org/W2063686821","doi":"https://doi.org/10.1142/s0218126615500425","title":"Logic Decomposition for PAL-Based CPLDs","display_name":"Logic Decomposition for PAL-Based CPLDs","publication_year":2014,"publication_date":"2014-12-15","ids":{"openalex":"https://openalex.org/W2063686821","doi":"https://doi.org/10.1142/s0218126615500425","mag":"2063686821"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126615500425","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615500425","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040131766","display_name":"Dariusz Kania","orcid":"https://orcid.org/0000-0002-3677-9939"},"institutions":[{"id":"https://openalex.org/I119004910","display_name":"Silesian University of Technology","ror":"https://ror.org/02dyjk442","country_code":"PL","type":"education","lineage":["https://openalex.org/I119004910"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Dariusz Kania","raw_affiliation_strings":["Silesian University of Technology, Institute of Electronics, ul. Akademicka 16, 44-100 Gliwice, Poland","Silesian University of Technology, Institute of Electronics; ul. Akademicka 16, 44-100 Gliwice, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silesian University of Technology, Institute of Electronics, ul. Akademicka 16, 44-100 Gliwice, Poland","institution_ids":["https://openalex.org/I119004910"]},{"raw_affiliation_string":"Silesian University of Technology, Institute of Electronics; ul. Akademicka 16, 44-100 Gliwice, Poland","institution_ids":["https://openalex.org/I119004910"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5040131766"],"corresponding_institution_ids":["https://openalex.org/I119004910"],"apc_list":null,"apc_paid":null,"fwci":1.0721,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.78383575,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"24","issue":"03","first_page":"1550042","last_page":"1550042"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.860680103302002},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.768287181854248},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6444810032844543},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.6366410851478577},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.6172986030578613},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6030025482177734},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.567277729511261},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5163336992263794},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5097514986991882},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.504970133304596},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4652816653251648},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.46315306425094604},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.45997002720832825},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45021679997444153},{"id":"https://openalex.org/keywords/decomposition-method","display_name":"Decomposition method (queueing theory)","score":0.4366971254348755},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4231153428554535},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4219846725463867},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4110524654388428},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3775225281715393},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.36733877658843994},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30119261145591736},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2811426520347595},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.1044912040233612}],"concepts":[{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.860680103302002},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.768287181854248},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6444810032844543},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.6366410851478577},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.6172986030578613},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6030025482177734},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.567277729511261},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5163336992263794},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5097514986991882},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.504970133304596},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4652816653251648},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.46315306425094604},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.45997002720832825},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45021679997444153},{"id":"https://openalex.org/C2778258933","wikidata":"https://www.wikidata.org/wiki/Q16918986","display_name":"Decomposition method (queueing theory)","level":2,"score":0.4366971254348755},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4231153428554535},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4219846725463867},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4110524654388428},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3775225281715393},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.36733877658843994},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30119261145591736},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2811426520347595},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.1044912040233612},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126615500425","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615500425","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1517096063","https://openalex.org/W1549045376","https://openalex.org/W1963953684","https://openalex.org/W1995135231","https://openalex.org/W2025013117","https://openalex.org/W2025851490","https://openalex.org/W2035847677","https://openalex.org/W2052014303","https://openalex.org/W2057209099","https://openalex.org/W2060729308","https://openalex.org/W2095565427","https://openalex.org/W2104032547","https://openalex.org/W2115731525","https://openalex.org/W2115967254","https://openalex.org/W2118988958","https://openalex.org/W2143784182","https://openalex.org/W2151927748","https://openalex.org/W2156801171","https://openalex.org/W2160564675","https://openalex.org/W2620411652"],"related_works":["https://openalex.org/W3013792460","https://openalex.org/W1904803855","https://openalex.org/W2376859467","https://openalex.org/W2990957507","https://openalex.org/W2374125170","https://openalex.org/W2118828191","https://openalex.org/W2139569078","https://openalex.org/W2047993371","https://openalex.org/W2134262422","https://openalex.org/W2120397377"],"abstract_inverted_index":{"The":[0,20,80],"Programmable":[1,16],"Array":[2],"Logic":[3,17],"(PAL)-based":[4],"logic":[5,48,78,93],"block":[6],"is":[7,25,54,64,73,85,124],"the":[8,11,43,55,58,89,98,103,110,120,128,132,146],"core":[9],"of":[10,14,22,30,38,45,57,82,91,105,115,127,140,154,162],"great":[12],"majority":[13],"Complex":[15],"Devices":[18],"(CPLDs).":[19],"purpose":[21],"this":[23],"paper":[24],"to":[26,33,42,101,136,145],"compare":[27],"two":[28,116],"models":[29,84,118],"decomposition":[31,62,83,117],"dedicated":[32],"PAL-based":[34,47,70,77,92,106,155],"devices.":[35],"Non-standard":[36],"usage":[37],"decomposition,":[39],"which":[40],"leads":[41],"reduction":[44,139],"used":[46,95],"blocks":[49,94,107,156],"in":[50,68,143],"a":[51,69,76,113,137,158],"programmable":[52],"structure,":[53],"aim":[56],"presented":[59],"methods.":[60],"Each":[61],"step":[63],"optimized":[65],"for":[66],"implementation":[67,122],"structure":[71],"that":[72,131],"characterized":[74],"by":[75],"block.":[79],"essence":[81],"oriented":[86],"towards":[87],"minimizing":[88],"number":[90,161],"and":[96],"adjusting":[97],"designed":[99],"circuit":[100],"fit":[102],"structures":[104,152],"best.":[108],"In":[109],"experimental":[111],"section,":[112],"comparison":[114],"with":[119],"classical":[121,147],"approach":[123],"presented.":[125],"Results":[126],"experiments":[129],"prove":[130],"proposed":[133],"methods":[134],"lead":[135],"significant":[138],"chip":[141],"area":[142],"relation":[144],"approach,":[148],"especially":[149],"if":[150],"CPLD":[151],"consist":[153],"containing":[157],"relatively":[159],"small":[160],"product":[163],"terms.":[164]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}