{"id":"https://openalex.org/W2080587764","doi":"https://doi.org/10.1142/s0218126615500371","title":"FPGA-Based Design \u0394\u2013\u03a3 Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit","display_name":"FPGA-Based Design \u0394\u2013\u03a3 Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit","publication_year":2014,"publication_date":"2014-12-10","ids":{"openalex":"https://openalex.org/W2080587764","doi":"https://doi.org/10.1142/s0218126615500371","mag":"2080587764"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126615500371","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615500371","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076465634","display_name":"Noura Ben Ameur","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131288","display_name":"National Engineering School of Tunis","ror":"https://ror.org/03b1zjt31","country_code":"TN","type":"education","lineage":["https://openalex.org/I4210131288","https://openalex.org/I63596082"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Noura Ben Ameur","raw_affiliation_strings":["Department of Electrical Engineering, National Engineering School, Soukra Street, Sfax 3038, Tunisia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Engineering School, Soukra Street, Sfax 3038, Tunisia","institution_ids":["https://openalex.org/I4210131288"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109201405","display_name":"Nouri Masmoudi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nouri Masmoudi","raw_affiliation_strings":["Electronics and Communication Research Group, Laboratory of Electronics and Information Technology, Soukra Street, Sfax 3038, Tunisia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Communication Research Group, Laboratory of Electronics and Information Technology, Soukra Street, Sfax 3038, Tunisia","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105939361","display_name":"Mourad Loulou","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mourad Loulou","raw_affiliation_strings":["Analogue, Mixed Mode and RF Design Group, Laboratory of Electronics and Information Technology, Sour Street, Sfax 3038, Tunisia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Analogue, Mixed Mode and RF Design Group, Laboratory of Electronics and Information Technology, Sour Street, Sfax 3038, Tunisia","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.11595991,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"24","issue":"03","first_page":"1550037","last_page":"1550037"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.9051219820976257},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8099931478500366},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.757743775844574},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5865249037742615},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5507380962371826},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5241841673851013},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.47380131483078003},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.42331552505493164},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3930455446243286},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3775556981563568},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3468138873577118},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21841692924499512}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.9051219820976257},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8099931478500366},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.757743775844574},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5865249037742615},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5507380962371826},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5241841673851013},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.47380131483078003},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.42331552505493164},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3930455446243286},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3775556981563568},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3468138873577118},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21841692924499512},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126615500371","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126615500371","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W95401678","https://openalex.org/W118952169","https://openalex.org/W2105664689"],"related_works":["https://openalex.org/W2129508730","https://openalex.org/W1843355381","https://openalex.org/W1530924151","https://openalex.org/W2534549730","https://openalex.org/W1964556228","https://openalex.org/W1873290954","https://openalex.org/W2167874369","https://openalex.org/W9221892","https://openalex.org/W2622383884","https://openalex.org/W2363829830"],"abstract_inverted_index":{"This":[0],"paper,":[1],"focus":[2],"on":[3],"synthesis":[4],"design":[5,25,38,64,85],"of":[6,77,83],"a":[7,23],"\u0394\u2013\u03a3":[8],"digital-to-analog":[9],"converter":[10],"(DAC)":[11],"algorithm":[12],"intended":[13],"for":[14,67],"professional":[15],"digital":[16],"audio.":[17],"A":[18,57],"rapid":[19],"register-transfer-level":[20],"(RTL)":[21],"using":[22],"top-down":[24],"method":[26],"with":[27,97],"VHSIC":[28],"hardware":[29],"description":[30],"language":[31],"(VHDL)":[32],"is":[33,95],"practiced.":[34],"All":[35],"the":[36,55,74,78,84,98],"RTL":[37],"simulation,":[39],"VHDL":[40],"implementation":[41],"and":[42,51,61,69,90],"field":[43],"programmable":[44],"gate":[45],"array":[46],"(FPGA)":[47],"verification":[48],"are":[49,65,86],"rapidly":[50],"systematically":[52],"performed":[53],"through":[54],"methodology.":[56],"distributed":[58],"pipelining,":[59],"streaming":[60],"resource":[62],"sharing":[63],"considered":[66],"area":[68],"speed":[70],"optimization":[71],"while":[72],"maintaining":[73],"original":[75],"precision":[76],"audio":[79],"DAC.":[80],"The":[81,92],"features":[82],"high-precision,":[87],"fast":[88],"processing":[89],"low-cost.":[91],"related":[93],"work":[94],"done":[96],"MATLAB":[99],"&":[100],"QUARTUS":[101],"II":[102],"simulators.":[103]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}
