{"id":"https://openalex.org/W2080482360","doi":"https://doi.org/10.1142/s0218126613500205","title":"UNIFICATION OF PR REGION FLOORPLANNING AND FINE-GRAINED PLACEMENT FOR DYNAMIC PARTIALLY RECONFIGURABLE FPGAS","display_name":"UNIFICATION OF PR REGION FLOORPLANNING AND FINE-GRAINED PLACEMENT FOR DYNAMIC PARTIALLY RECONFIGURABLE FPGAS","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W2080482360","doi":"https://doi.org/10.1142/s0218126613500205","mag":"2080482360"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126613500205","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126613500205","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046766246","display_name":"Ruining He","orcid":"https://orcid.org/0000-0003-0346-7311"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"RUINING HE","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084882702","display_name":"Guoqiang Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"GUOQIANG LIANG","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102025379","display_name":"Yuchun Ma","orcid":"https://orcid.org/0000-0003-3160-6681"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"YUCHUN MA","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100445061","display_name":"Yu Wang","orcid":"https://orcid.org/0000-0001-6108-5157"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"YU WANG","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, 100084, China","Department of Electronic Engineering, Tsinghua University,#N#Beijing 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University,#N#Beijing 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034755987","display_name":"Jinian Bian","orcid":"https://orcid.org/0000-0002-4322-1503"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"JINIAN BIAN","raw_affiliation_strings":["Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5046766246"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.13882689,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"22","issue":"04","first_page":"1350020","last_page":"1350020"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9469375610351562},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8404196500778198},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6660363674163818},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6240588426589966},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5758503079414368},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.42439499497413635},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.40969860553741455},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33315587043762207},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3288838267326355},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15171480178833008},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10868924856185913}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9469375610351562},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8404196500778198},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6660363674163818},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6240588426589966},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5758503079414368},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.42439499497413635},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.40969860553741455},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33315587043762207},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3288838267326355},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15171480178833008},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10868924856185913},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126613500205","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126613500205","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W75974310","https://openalex.org/W1823959354","https://openalex.org/W2003903169","https://openalex.org/W2034729118","https://openalex.org/W2035847677","https://openalex.org/W2048672904","https://openalex.org/W2079543149","https://openalex.org/W2081381252","https://openalex.org/W2098983317","https://openalex.org/W2120763018","https://openalex.org/W2139637699","https://openalex.org/W2180598069"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W2180598069","https://openalex.org/W2797161794","https://openalex.org/W2096938998","https://openalex.org/W1760305469","https://openalex.org/W2385177848"],"abstract_inverted_index":{"Dynamic":[0],"Partially":[1,38],"Reconfiguration":[2],"(DPR)":[3],"designs":[4,117],"provide":[5],"additional":[6],"benefits":[7],"compared":[8,223],"to":[9,15,30,73,83,91,118,188,224],"traditional":[10],"FPGA":[11],"application.":[12],"However,":[13],"due":[14,187],"the":[16,33,56,65,93,97,120,145,189,193],"lack":[17],"of":[18,37,96,195],"support":[19],"from":[20,192],"automatic":[21],"design":[22,26,227],"tools":[23],"in":[24,166,180],"current":[25,225],"flow,":[27],"designers":[28],"have":[29],"manually":[31],"define":[32],"dimensions":[34],"and":[35,70,108,126,134,174,199,218],"positions":[36],"Reconfigurable":[39],"Regions":[40,125],"(PR":[41],"Regions).":[42],"The":[43],"following":[44],"fine-grained":[45,75,89,200],"placement":[46,76,90],"for":[47,103,115,122,138],"system":[48,140],"modules":[49],"is":[50,68],"also":[51,144],"limited":[52],"because":[53],"it":[54],"takes":[55],"floorplanning":[57,67,87,107,173,198],"result":[58],"as":[59],"a":[60,157],"rigid":[61],"region":[62],"constraint.":[63],"Therefore,":[64],"manual":[66],"laborious":[69],"may":[71],"lead":[72],"inferior":[74],"results.":[77],"In":[78],"this":[79],"paper,":[80],"we":[81,155],"propose":[82],"integrate":[84],"PR":[85,105,124,196],"Region":[86,106,197],"with":[88],"achieve":[92],"global":[94,175],"optimization":[95,160,168,176],"whole":[98],"DPR":[99,116,139,226],"system.":[100],"Effective":[101],"strategies":[102],"tuning":[104],"apposite":[109],"analytical":[110],"evaluation":[111],"models":[112],"are":[113,141],"customized":[114],"handle":[119],"co-optimization":[121],"both":[123],"static":[127],"region.":[128],"Not":[129],"only":[130],"practical":[131],"reconfiguration":[132,136,213],"cost":[133],"specific":[135],"constraints":[137],"considered,":[142],"but":[143],"congestion":[146],"estimation":[147],"can":[148,177,204],"be":[149,178],"relaxed":[150],"by":[151],"our":[152,202],"approach.":[153],"Especially,":[154],"established":[156],"two-stage":[158],"stochastic":[159],"framework":[161],"which":[162],"handles":[163],"different":[164,167],"objectives":[165],"stages":[169],"so":[170],"that":[171,186],"automated":[172],"achieved":[179],"reasonable":[181],"time.":[182],"Experimental":[183],"results":[184],"demonstrate":[185],"flexibility":[190],"benefit":[191],"unification":[194],"placement,":[201],"approach":[203],"improve":[205],"20.9%":[206],"on":[207,212,216,220],"critical":[208],"path":[209],"delay,":[210,214],"24%":[211],"12%":[215],"congestion,":[217],"8.7%":[219],"wire":[221],"length":[222],"method.":[228]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
