{"id":"https://openalex.org/W2156594066","doi":"https://doi.org/10.1142/s0218126613400252","title":"A NOVEL DECOMPOSITION APPROACH AND VLSI IMPLEMENTATION OF CHROMA INTERPOLATOR FOR H.264 ENCODERS","display_name":"A NOVEL DECOMPOSITION APPROACH AND VLSI IMPLEMENTATION OF CHROMA INTERPOLATOR FOR H.264 ENCODERS","publication_year":2013,"publication_date":"2013-11-17","ids":{"openalex":"https://openalex.org/W2156594066","doi":"https://doi.org/10.1142/s0218126613400252","mag":"2156594066"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126613400252","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126613400252","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089778019","display_name":"Teng Wang","orcid":"https://orcid.org/0000-0003-3729-0139"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"TENG WANG","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011960711","display_name":"Lei Zhao","orcid":"https://orcid.org/0000-0003-4497-2197"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"LEI ZHAO","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102171012","display_name":"Ziyi Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"ZI-YI HU","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047765511","display_name":"Zheng Xie","orcid":"https://orcid.org/0000-0003-0391-8725"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"ZHENG XIE","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102009435","display_name":"Xin\u2019an Wang","orcid":"https://orcid.org/0000-0002-9712-8531"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"XIN-AN WANG","raw_affiliation_strings":["Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Integrated Microsystem Science and Engineering Applications, Peking University Shenzhen Graduate School, No. 2199, Lishui Road, Nanshan, Shenzhen 518055, P. R. China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5102009435"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18405737,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"22","issue":"10","first_page":"1340025","last_page":"1340025"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6800601482391357},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6609092950820923},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6478103995323181},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.6401990056037903},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.6137670278549194},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5756138563156128},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5252620577812195},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4821983873844147},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.45561206340789795},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43724310398101807},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.4131099283695221},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37568655610084534},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34310483932495117},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.33830809593200684},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.2759115695953369},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.18735969066619873},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14064371585845947},{"id":"https://openalex.org/keywords/computer-graphics","display_name":"Computer graphics (images)","score":0.12405714392662048},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10485142469406128}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6800601482391357},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6609092950820923},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6478103995323181},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.6401990056037903},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.6137670278549194},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5756138563156128},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5252620577812195},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4821983873844147},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.45561206340789795},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43724310398101807},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.4131099283695221},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37568655610084534},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34310483932495117},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.33830809593200684},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.2759115695953369},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.18735969066619873},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14064371585845947},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.12405714392662048},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10485142469406128},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C502989409","wikidata":"https://www.wikidata.org/wiki/Q11425","display_name":"Animation","level":2,"score":0.0},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126613400252","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126613400252","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1569235285","https://openalex.org/W2113948920","https://openalex.org/W2121840029","https://openalex.org/W2138006056","https://openalex.org/W2140199336","https://openalex.org/W2142022974","https://openalex.org/W2146029364","https://openalex.org/W2171203958"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W2015155483","https://openalex.org/W2163915119","https://openalex.org/W1572837867","https://openalex.org/W2141748053","https://openalex.org/W2031051084"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,66,87,93,114,123],"novel":[4],"decomposition":[5,39],"approach":[6],"and":[7,18,65,131],"VLSI":[8],"implementation":[9],"of":[10,29,56,61,117],"the":[11,27,30,43,74],"chroma":[12,31,44,75],"interpolator":[13],"with":[14,41,49,77,92,107,113,127],"great":[15,78],"hardware":[16,68,79,129],"reuse":[17],"no":[19],"multipliers":[20],"for":[21],"H.264":[22],"encoders":[23],"are":[24,54,63],"proposed.":[25],"First,":[26],"characteristic":[28],"interpolation":[32,45,76],"is":[33,70],"analyzed":[34],"to":[35,72],"obtain":[36],"an":[37],"optimized":[38],"scheme,":[40],"which":[42,53,120],"can":[46],"be":[47],"realized":[48],"arithmetic":[50],"elements":[51],"(AEs)":[52],"comprised":[55],"only":[57],"adders.":[58],"Four":[59],"types":[60],"AEs":[62],"developed":[64],"pipelining":[67],"design":[69,83,103],"proposed":[71,82,102],"conduct":[73],"reuse.":[80],"The":[81,101],"was":[84,104],"prototyped":[85],"within":[86],"Xilinx":[88],"Virtex6":[89],"XC6VLX240T":[90],"FPGA":[91],"clock":[94,115],"frequency":[95,116],"as":[96,98],"high":[97],"245":[99],"MHz.":[100],"also":[105],"synthesized":[106],"SMIC":[108],"130":[109],"nm":[110],"CMOS":[111],"technology":[112],"200":[118],"MHz,":[119],"could":[121],"support":[122],"real-time":[124],"HDTV":[125],"application":[126],"less":[128],"cost":[130],"lower":[132],"power":[133],"consumption.":[134]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}