{"id":"https://openalex.org/W2065743933","doi":"https://doi.org/10.1142/s021812661240018x","title":"AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE","display_name":"AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W2065743933","doi":"https://doi.org/10.1142/s021812661240018x","mag":"2065743933"},"language":"en","primary_location":{"id":"doi:10.1142/s021812661240018x","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s021812661240018x","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070434816","display_name":"Yousri Ouerhani","orcid":null},"institutions":[{"id":"https://openalex.org/I3132279224","display_name":"Institut Sup\u00e9rieur de l'\u00c9lectronique et du Num\u00e9rique","ror":"https://ror.org/017h2rd72","country_code":"FR","type":"education","lineage":["https://openalex.org/I3132279224"]}],"countries":["FR"],"is_corresponding":true,"raw_author_name":"YOUSRI OUERHANI","raw_affiliation_strings":["Equipe Vision, Laboratoire L@bISEN de ISEN-Brest, 20 Rue Cuirasse Bretagne, CS 42807, 29228 Brest Cedex 2, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Equipe Vision, Laboratoire L@bISEN de ISEN-Brest, 20 Rue Cuirasse Bretagne, CS 42807, 29228 Brest Cedex 2, France","institution_ids":["https://openalex.org/I3132279224"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090388480","display_name":"Maher Jridi","orcid":"https://orcid.org/0000-0002-9316-7920"},"institutions":[{"id":"https://openalex.org/I3132279224","display_name":"Institut Sup\u00e9rieur de l'\u00c9lectronique et du Num\u00e9rique","ror":"https://ror.org/017h2rd72","country_code":"FR","type":"education","lineage":["https://openalex.org/I3132279224"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"MAHER JRIDI","raw_affiliation_strings":["Equipe Vision, Laboratoire L@bISEN de ISEN-Brest, 20 Rue Cuirasse Bretagne, CS 42807, 29228 Brest Cedex 2, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Equipe Vision, Laboratoire L@bISEN de ISEN-Brest, 20 Rue Cuirasse Bretagne, CS 42807, 29228 Brest Cedex 2, France","institution_ids":["https://openalex.org/I3132279224"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038885367","display_name":"Ayman Alfalou","orcid":"https://orcid.org/0000-0002-3965-4648"},"institutions":[{"id":"https://openalex.org/I3132279224","display_name":"Institut Sup\u00e9rieur de l'\u00c9lectronique et du Num\u00e9rique","ror":"https://ror.org/017h2rd72","country_code":"FR","type":"education","lineage":["https://openalex.org/I3132279224"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"AYMAN ALFALOU","raw_affiliation_strings":["Equipe Vision, Laboratoire L@bISEN de ISEN-Brest, 20 Rue Cuirasse Bretagne, CS 42807, 29228 Brest Cedex 2, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Equipe Vision, Laboratoire L@bISEN de ISEN-Brest, 20 Rue Cuirasse Bretagne, CS 42807, 29228 Brest Cedex 2, France","institution_ids":["https://openalex.org/I3132279224"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5070434816"],"corresponding_institution_ids":["https://openalex.org/I3132279224"],"apc_list":null,"apc_paid":null,"fwci":0.4952,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.67524828,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"21","issue":"06","first_page":"1240018","last_page":"1240018"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7605544328689575},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7584054470062256},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7537845373153687},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5799857378005981},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5760310292243958},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5567262768745422},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.47816330194473267},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.383236825466156},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3609161376953125},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33789148926734924},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17875126004219055}],"concepts":[{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7605544328689575},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7584054470062256},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7537845373153687},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5799857378005981},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5760310292243958},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5567262768745422},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.47816330194473267},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.383236825466156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3609161376953125},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33789148926734924},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17875126004219055},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1142/s021812661240018x","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s021812661240018x","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},{"id":"pmh:oai:HAL:hal-03105185v1","is_oa":false,"landing_page_url":"https://hal.science/hal-03105185","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Journal of Circuits, Systems, and Computers, 2012, 21 (06), pp.1240018. &#x27E8;10.1142/S021812661240018X&#x27E9;","raw_type":"Journal articles"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1486092146","https://openalex.org/W1587168362","https://openalex.org/W1766888123","https://openalex.org/W1900969659","https://openalex.org/W1923763959","https://openalex.org/W1977482330","https://openalex.org/W1985765205","https://openalex.org/W1996782408","https://openalex.org/W2015346536","https://openalex.org/W2020141429","https://openalex.org/W2029360173","https://openalex.org/W2036812077","https://openalex.org/W2054253789","https://openalex.org/W2061171222","https://openalex.org/W2068728216","https://openalex.org/W2097772361","https://openalex.org/W2108208195","https://openalex.org/W2110872491","https://openalex.org/W2111755292","https://openalex.org/W2135090308","https://openalex.org/W2141427150","https://openalex.org/W2145277692","https://openalex.org/W2152992780","https://openalex.org/W2170967482","https://openalex.org/W2478884216"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4327521644","https://openalex.org/W3132558499","https://openalex.org/W2978884468","https://openalex.org/W2005846134","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"In":[0,31],"this":[1],"paper":[2],"we":[3,110],"present":[4],"a":[5,24,38,65,107],"novel":[6],"architecture":[7,15,53],"for":[8,141],"FFT":[9,57],"implementation":[10],"on":[11,17,36],"FPGA.":[12],"The":[13,51],"proposed":[14,52,98,114],"based":[16],"radix-4":[18],"algorithm":[19],"presents":[20],"the":[21,33,84,94,97,102,113,136],"advantage":[22],"of":[23,67,73,96,120,133],"higher":[25],"throughput":[26,137],"and":[27,41,63,76,86,130],"low":[28],"area-delay":[29,77],"product.":[30],"fact,":[32],"novelty":[34],"consists":[35],"using":[37,58],"memory":[39],"sharing":[40],"dividing":[42],"technique":[43],"along":[44],"with":[45,79,126],"parallel-in":[46],"parallel-out":[47],"Processing":[48],"Elements":[49],"(PE).":[50],"can":[54],"perform":[55],"N-point":[56],"only":[59],"4/3N":[60],"delay":[61],"elements":[62],"involves":[64,116],"latency":[66],"N/4":[68],"cycles.":[69],"Comparison":[70],"in":[71,83,135],"terms":[72],"hardware":[74],"complexity":[75],"product":[78],"recent":[80],"works":[81],"presented":[82],"literature":[85],"commercial":[87],"IPs":[88],"has":[89],"been":[90],"made":[91],"to":[92],"show":[93],"efficiency":[95],"design.":[99],"Moreover,":[100],"from":[101,106],"experimental":[103],"results":[104],"obtained":[105,125],"FPGA":[108],"prototype":[109],"find":[111],"that":[112,124],"design":[115],"an":[117,131],"execution":[118],"time":[119],"56%":[121],"lower":[122],"than":[123],"Xilinx":[127],"IP":[128],"core":[129],"increase":[132],"19%":[134],"by":[138],"area":[139],"ratio":[140],"256-point":[142],"FFT.":[143]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-05-21T09:19:25.381259","created_date":"2025-10-10T00:00:00"}
