{"id":"https://openalex.org/W2041835814","doi":"https://doi.org/10.1142/s0218126611007281","title":"CASCADABLE ALL-PASS AND NOTCH FILTER CONFIGURATIONS EMPLOYING TWO PLUS-TYPE DDCCs","display_name":"CASCADABLE ALL-PASS AND NOTCH FILTER CONFIGURATIONS EMPLOYING TWO PLUS-TYPE DDCCs","publication_year":2011,"publication_date":"2011-03-10","ids":{"openalex":"https://openalex.org/W2041835814","doi":"https://doi.org/10.1142/s0218126611007281","mag":"2041835814"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126611007281","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126611007281","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049755553","display_name":"Sudhanshu Maheshwari","orcid":"https://orcid.org/0000-0003-4727-022X"},"institutions":[{"id":"https://openalex.org/I171210897","display_name":"Aligarh Muslim University","ror":"https://ror.org/03kw9gc02","country_code":"IN","type":"education","lineage":["https://openalex.org/I171210897"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"SUDHANSHU MAHESHWARI","raw_affiliation_strings":["Department of Electronics Engineering, Z. H. College of Engineering and Technology, Aligarh Muslim University, Aligarh-202002, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, Z. H. College of Engineering and Technology, Aligarh Muslim University, Aligarh-202002, India","institution_ids":["https://openalex.org/I171210897"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055012514","display_name":"Jitendra Mohan","orcid":"https://orcid.org/0000-0001-7159-3665"},"institutions":[{"id":"https://openalex.org/I153954893","display_name":"Jaypee University of Information Technology","ror":"https://ror.org/00hshrf16","country_code":"IN","type":"education","lineage":["https://openalex.org/I153954893"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"JITENDRA MOHAN","raw_affiliation_strings":["Department of Electronics and Communications, Jaypee University of Information Technology, Waknaghat, Solan-173215, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communications, Jaypee University of Information Technology, Waknaghat, Solan-173215, India","institution_ids":["https://openalex.org/I153954893"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101659805","display_name":"Durg Singh Chauhan","orcid":"https://orcid.org/0000-0002-9076-0665"},"institutions":[{"id":"https://openalex.org/I91357014","display_name":"Banaras Hindu University","ror":"https://ror.org/04cdn2797","country_code":"IN","type":"education","lineage":["https://openalex.org/I91357014"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"DURG SINGH CHAUHAN","raw_affiliation_strings":["Department of Electrical Engineering, Institute of Technology, Banaras Hindu University, Varanasi-221005, India","Department of Electrical Engineering, Institute of Technology, Banaras Hindu University, Varanasi 221005, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Institute of Technology, Banaras Hindu University, Varanasi-221005, India","institution_ids":["https://openalex.org/I91357014"]},{"raw_affiliation_string":"Department of Electrical Engineering, Institute of Technology, Banaras Hindu University, Varanasi 221005, India#TAB#","institution_ids":["https://openalex.org/I91357014"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5049755553"],"corresponding_institution_ids":["https://openalex.org/I171210897"],"apc_list":null,"apc_paid":null,"fwci":1.6788,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.83237919,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"20","issue":"02","first_page":"329","last_page":"347"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.6882051229476929},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.6701174378395081},{"id":"https://openalex.org/keywords/output-impedance","display_name":"Output impedance","score":0.5712389945983887},{"id":"https://openalex.org/keywords/electrical-impedance","display_name":"Electrical impedance","score":0.5375760197639465},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49445247650146484},{"id":"https://openalex.org/keywords/low-pass-filter","display_name":"Low-pass filter","score":0.49414756894111633},{"id":"https://openalex.org/keywords/high-impedance","display_name":"High impedance","score":0.47691699862480164},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45292818546295166},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.4502793550491333},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4365103840827942},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.43211138248443604},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.4203481674194336},{"id":"https://openalex.org/keywords/band-stop-filter","display_name":"Band-stop filter","score":0.4146055579185486},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33406203985214233},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3227742314338684},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2723546028137207},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14951840043067932}],"concepts":[{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.6882051229476929},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.6701174378395081},{"id":"https://openalex.org/C58112919","wikidata":"https://www.wikidata.org/wiki/Q631203","display_name":"Output impedance","level":3,"score":0.5712389945983887},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.5375760197639465},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49445247650146484},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.49414756894111633},{"id":"https://openalex.org/C174268685","wikidata":"https://www.wikidata.org/wiki/Q769127","display_name":"High impedance","level":3,"score":0.47691699862480164},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45292818546295166},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.4502793550491333},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4365103840827942},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.43211138248443604},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.4203481674194336},{"id":"https://openalex.org/C112806600","wikidata":"https://www.wikidata.org/wiki/Q386022","display_name":"Band-stop filter","level":4,"score":0.4146055579185486},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33406203985214233},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3227742314338684},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2723546028137207},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14951840043067932},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126611007281","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126611007281","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8199999928474426,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1966914807","https://openalex.org/W1969172442","https://openalex.org/W1970203984","https://openalex.org/W1979337577","https://openalex.org/W1985264417","https://openalex.org/W1990252036","https://openalex.org/W1992023063","https://openalex.org/W1997485355","https://openalex.org/W2006946992","https://openalex.org/W2044255284","https://openalex.org/W2059055117","https://openalex.org/W2061382773","https://openalex.org/W2067280905","https://openalex.org/W2074153736","https://openalex.org/W2075824720","https://openalex.org/W2084345925","https://openalex.org/W2095937120","https://openalex.org/W2113493322","https://openalex.org/W2116161142","https://openalex.org/W2121265045","https://openalex.org/W2122620836","https://openalex.org/W2125666370","https://openalex.org/W2132027356","https://openalex.org/W2163466077","https://openalex.org/W2166282944","https://openalex.org/W2332673951","https://openalex.org/W4254839687"],"related_works":["https://openalex.org/W2165578448","https://openalex.org/W4226537602","https://openalex.org/W2104827668","https://openalex.org/W1583031430","https://openalex.org/W2105842058","https://openalex.org/W2088773460","https://openalex.org/W2390887431","https://openalex.org/W2392313090","https://openalex.org/W2033967487","https://openalex.org/W2803782676"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"twelve":[3],"new":[4],"circuit":[5,29],"configurations":[6,30],"for":[7,49,61],"realization":[8],"of":[9,73],"first-order,":[10],"second-order":[11,63],"voltage-mode":[12],"all-pass":[13,52],"and":[14,21,36,45,54,58,69],"notch":[15],"filters":[16],"with":[17,98],"high":[18],"input":[19,67],"impedance":[20,24,68,72],"low":[22,70],"output":[23,71],"are":[25,96],"presented.":[26],"The":[27,39,93],"proposed":[28],"use":[31,41],"two":[32,37,46,55,59],"plus":[33],"type":[34],"DDCCs,":[35],"impedances.":[38],"circuits":[40,78],"one":[42],"grounded":[43,47,56],"capacitor":[44],"resistors":[48,60],"realizing":[50,62],"first-order":[51],"filters,":[53],"capacitors":[57],"all-pass/notch":[64],"filters.":[65],"High":[66],"the":[74,77],"configuration":[75],"enable":[76],"to":[79],"be":[80],"cascaded":[81],"without":[82],"additional":[83],"buffers.":[84],"As":[85],"an":[86],"application,":[87],"a":[88],"quadrature":[89],"oscillator":[90],"is":[91],"realized.":[92],"theoretical":[94],"results":[95],"verified":[97],"PSPICE":[99],"simulations":[100],"using":[101],"0.5":[102],"\u03bcm":[103],"CMOS":[104],"parameters.":[105]},"counts_by_year":[{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
