{"id":"https://openalex.org/W2119501440","doi":"https://doi.org/10.1142/s0218126607003484","title":"A HIGH FLEXIBILITY DESIGN FOR CLOCK DISTRIBUTION NETWORK IN SYSTEM ON CHIP","display_name":"A HIGH FLEXIBILITY DESIGN FOR CLOCK DISTRIBUTION NETWORK IN SYSTEM ON CHIP","publication_year":2007,"publication_date":"2007-02-01","ids":{"openalex":"https://openalex.org/W2119501440","doi":"https://doi.org/10.1142/s0218126607003484","mag":"2119501440"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126607003484","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126607003484","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055151952","display_name":"Chi\u2010Chou Kao","orcid":"https://orcid.org/0000-0003-3174-9367"},"institutions":[{"id":"https://openalex.org/I1309796872","display_name":"National Pingtung University","ror":"https://ror.org/03z698x91","country_code":"TW","type":"education","lineage":["https://openalex.org/I1309796872"]},{"id":"https://openalex.org/I16566446","display_name":"National Pingtung University of Science and Technology","ror":"https://ror.org/01y6ccj36","country_code":"TW","type":"education","lineage":["https://openalex.org/I16566446"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"CHI-CHOU KAO","raw_affiliation_strings":["Department of Information Technology, National Pingtung Institute of Commerce, Pingtung 900, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"Department of Information Technology, National Pingtung Institute of Commerce, Pingtung 900, Taiwan, R.O.C","institution_ids":["https://openalex.org/I16566446","https://openalex.org/I1309796872"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5055151952"],"corresponding_institution_ids":["https://openalex.org/I1309796872","https://openalex.org/I16566446"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15271369,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"16","issue":"01","first_page":"51","last_page":"63"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.6917904615402222},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6560072898864746},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6414565443992615},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.549085795879364},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.541948676109314},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5359753966331482},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5266347527503967},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5242660045623779},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.505462646484375},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.475195050239563},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4722259044647217},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4685218036174774},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4372081160545349},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.43299058079719543},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4158942401409149},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3504266142845154},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12449553608894348},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11458921432495117},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.11006280779838562}],"concepts":[{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.6917904615402222},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6560072898864746},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6414565443992615},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.549085795879364},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.541948676109314},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5359753966331482},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5266347527503967},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5242660045623779},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.505462646484375},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.475195050239563},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4722259044647217},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4685218036174774},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4372081160545349},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.43299058079719543},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4158942401409149},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3504266142845154},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12449553608894348},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11458921432495117},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.11006280779838562},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218126607003484","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126607003484","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4000000059604645}],"awards":[],"funders":[{"id":"https://openalex.org/F4320324663","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1502296014","https://openalex.org/W1984588379","https://openalex.org/W2082603453","https://openalex.org/W2085394932","https://openalex.org/W2116382776","https://openalex.org/W2119986070","https://openalex.org/W2122533670","https://openalex.org/W2128237591","https://openalex.org/W2131239505","https://openalex.org/W2136768070","https://openalex.org/W2148609278","https://openalex.org/W2148880055","https://openalex.org/W2154363431","https://openalex.org/W2490203607"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2137310043","https://openalex.org/W3006003651","https://openalex.org/W2337711143","https://openalex.org/W4313332229","https://openalex.org/W2090213929","https://openalex.org/W2169618112"],"abstract_inverted_index":{"The":[0,31,140],"idea":[1],"of":[2,26,37,48,106,125,146],"combining":[3],"high-speed":[4],"digital":[5],"cores,":[6],"memory":[7],"arrays,":[8],"analog":[9],"blocks,":[10],"and":[11,104,135],"communication":[12],"circuitry":[13],"onto":[14],"a":[15,21,45,55,126],"single":[16],"chip":[17],"has":[18],"led":[19],"to":[20,60,90],"whole":[22,123],"new":[23,98],"design":[24,129],"era":[25],"System":[27],"on":[28],"Chips":[29],"(SoCs).":[30],"clock":[32,63,71,94,102,137],"distribution":[33,64,72,95,118],"network":[34,65,119],"is":[35,58],"one":[36],"the":[38,49,62,70,84,92,101,117,122,132,144,147],"important":[39],"issues":[40],"in":[41,83],"SoCs":[42],"that":[43,109],"consumes":[44],"significant":[46],"portion":[47],"total":[50],"performance.":[51],"In":[52],"this":[53],"paper,":[54],"flexible":[56,67],"capacitance":[57],"used":[59],"make":[61],"more":[66],"for":[68],"designing":[69],"network.":[73,96],"Therefore,":[74],"if":[75],"some":[76],"IP":[77],"(intellectual":[78],"property)":[79],"cores":[80],"are":[81],"changed":[82],"system,":[85],"we":[86],"do":[87],"not":[88],"need":[89],"redesign":[91],"overall":[93],"This":[97,128],"approach":[99],"facilitates":[100],"timing":[103],"synchronization":[105],"IPs":[107,110],"so":[108],"can":[111],"be":[112],"inserted":[113],"or":[114],"removed":[115],"from":[116],"without":[120],"affecting":[121],"performance":[124],"SoC.":[127],"uses":[130],"efficiently":[131],"available":[133],"resources":[134],"maintains":[136],"signal":[138],"integrity.":[139],"experimental":[141],"results":[142],"confirm":[143],"efficiency":[145],"proposed":[148],"design.":[149]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}