{"id":"https://openalex.org/W2024924124","doi":"https://doi.org/10.1142/s0218126606003143","title":"SIZING CMOS INVERTERS WITH MILLER EFFECT AND THRESHOLD VOLTAGE VARIATIONS","display_name":"SIZING CMOS INVERTERS WITH MILLER EFFECT AND THRESHOLD VOLTAGE VARIATIONS","publication_year":2006,"publication_date":"2006-06-01","ids":{"openalex":"https://openalex.org/W2024924124","doi":"https://doi.org/10.1142/s0218126606003143","mag":"2024924124"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126606003143","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126606003143","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089119735","display_name":"Boris D. Andreev","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"BORIS ANDREEV","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003884564","display_name":"E.L. Titlebaum","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"EDWARD L. TITLEBAUM","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053517349","display_name":"Eby G. Friedman","orcid":"https://orcid.org/0000-0002-5549-7160"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"EBY G. FRIEDMAN","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627, USA","institution_ids":["https://openalex.org/I5388228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":null,"apc_paid":null,"fwci":0.3791,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.64422647,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"15","issue":"03","first_page":"437","last_page":"454"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6901766061782837},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.6364025473594666},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6360942125320435},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6148087382316589},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5447876453399658},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5304678678512573},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4844403564929962},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.43650922179222107},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38190144300460815},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.379558265209198},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3609667122364044},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2699047923088074},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2164052426815033}],"concepts":[{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6901766061782837},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.6364025473594666},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6360942125320435},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6148087382316589},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5447876453399658},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5304678678512573},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4844403564929962},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.43650922179222107},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38190144300460815},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.379558265209198},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3609667122364044},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2699047923088074},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2164052426815033},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1142/s0218126606003143","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126606003143","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.77.8842","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.77.8842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.rochester.edu/users/friedman/papers/JCSC_06.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1533614470","https://openalex.org/W1598341975","https://openalex.org/W1982756257","https://openalex.org/W1996623312","https://openalex.org/W2022892565","https://openalex.org/W2055510065","https://openalex.org/W2125414987"],"related_works":["https://openalex.org/W2030839013","https://openalex.org/W1980639873","https://openalex.org/W2947371407","https://openalex.org/W2147978085","https://openalex.org/W2008277438","https://openalex.org/W2896864107","https://openalex.org/W3130418065","https://openalex.org/W2965542777","https://openalex.org/W2153322834","https://openalex.org/W1936081522"],"abstract_inverted_index":{"The":[0,48,83],"maximum":[1],"speed":[2,31],"of":[3,63,85,103],"synchronous":[4],"circuits":[5],"is":[6,39,57,95,111],"generally":[7],"constrained":[8],"by":[9],"the":[10,17,26,42,58,61,64,71,74,78,86,101,114,118,122,127,133,137,181],"worst":[11],"case":[12],"propagation":[13],"delay,":[14,28],"which":[15,69],"limits":[16],"system":[18,34],"clock":[19],"frequency.":[20],"Various":[21],"techniques":[22],"exist":[23],"to":[24,40,88,139,142,179],"manage":[25],"circuit":[27,93,146,174],"trading":[29],"off":[30],"for":[32,52,91],"other":[33],"resources.":[35],"One":[36],"such":[37],"approach":[38],"equalize":[41],"rise":[43,105],"and":[44,66,80,106,117,132,164,171],"fall":[45,107],"delay":[46,55,108,130],"times.":[47,109],"primary":[49],"design":[50,175],"parameter":[51],"equalizing":[53],"these":[54],"times":[56,131],"ratio":[59,90,141],"between":[60,73,126],"width":[62],"PMOS":[65],"NMOS":[67],"transistors,":[68],"determines":[70],"relationship":[72,125],"currents":[75],"passed":[76],"along":[77],"pull-up":[79,87,138],"pull-down":[81,89,140],"paths.":[82],"variation":[84],"different":[92],"parameters":[94,147],"discussed":[96],"in":[97,155],"this":[98],"paper":[99],"under":[100],"constraint":[102],"equal":[104],"It":[110],"shown":[112],"that":[113],"short-circuit":[115],"current":[116],"Miller":[119,182],"capacitance":[120],"affect":[121],"ideal":[123],"linear":[124],"CMOS":[128],"inverter":[129],"load":[134],"capacitance,":[135],"requiring":[136],"be":[143],"adjusted":[144],"as":[145],"are":[148,152,177],"varied.":[149],"These":[150],"effects":[151],"more":[153],"pronounced":[154],"deep":[156],"submicrometer":[157],"technologies":[158],"with":[159],"significant":[160],"parasitic":[161],"MOSFET":[162],"capacitances":[163],"threshold":[165],"voltage":[166],"variations.":[167],"Based":[168],"on":[169],"analytic":[170],"experimental":[172],"observations,":[173],"guidelines":[176],"proposed":[178],"minimize":[180],"effect.":[183]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}