{"id":"https://openalex.org/W2039928778","doi":"https://doi.org/10.1142/s0218126606002927","title":"INFLUENCE OF INPUT/OUTPUT OPERATIONS ON PROCESSOR PERFORMANCE","display_name":"INFLUENCE OF INPUT/OUTPUT OPERATIONS ON PROCESSOR PERFORMANCE","publication_year":2006,"publication_date":"2006-02-01","ids":{"openalex":"https://openalex.org/W2039928778","doi":"https://doi.org/10.1142/s0218126606002927","mag":"2039928778"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126606002927","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126606002927","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5073294813","display_name":"Jos\u00e9 Mar\u00eda Rodr\u00edguez Corral","orcid":"https://orcid.org/0000-0003-1988-5702"},"institutions":[{"id":"https://openalex.org/I39147953","display_name":"Universidad de C\u00e1diz","ror":"https://ror.org/04mxxkb11","country_code":"ES","type":"education","lineage":["https://openalex.org/I39147953"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"JOSE MARIA RODR\u00cdGUEZ CORRAL","raw_affiliation_strings":["Lenguajes y Sistemas Inform\u00e1ticos, Universidad de C\u00e1diz, Escuela Superior de Ingenier\u00eda, C/Chile 1, 11003 C\u00e1diz, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lenguajes y Sistemas Inform\u00e1ticos, Universidad de C\u00e1diz, Escuela Superior de Ingenier\u00eda, C/Chile 1, 11003 C\u00e1diz, Spain","institution_ids":["https://openalex.org/I39147953"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059834579","display_name":"A Balcells","orcid":"https://orcid.org/0000-0001-8733-1811"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"ANTON CIVIT BALCELLS","raw_affiliation_strings":["Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012722971","display_name":"G. Jim\u00e9nez","orcid":"https://orcid.org/0000-0003-4512-6750"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"GABRIEL JIMENEZ MORENO","raw_affiliation_strings":["Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075163995","display_name":"Jos\u00e9 Luis Sevillano","orcid":"https://orcid.org/0000-0002-1392-1832"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"JOSE LUIS SEVILLANO RAMOS","raw_affiliation_strings":["Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s/n, 41012 Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022701624","display_name":"Arturo Morgado\u2010Est\u00e9vez","orcid":"https://orcid.org/0000-0002-3639-3649"},"institutions":[{"id":"https://openalex.org/I39147953","display_name":"Universidad de C\u00e1diz","ror":"https://ror.org/04mxxkb11","country_code":"ES","type":"education","lineage":["https://openalex.org/I39147953"]},{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"ARTURO MORGADO ESTEVEZ","raw_affiliation_strings":["Ingenier\u00eda de Sistemas y Autom\u00e1tica, Tecnolog\u00eda Electr\u00f3nica y Electr\u00f3nica, Universidad de C\u00e1diz, Escuela Superior de Ingenier\u00eda, C/Chile 1, 11003 C\u00e1diz, Spain","Universidad de Sevilla"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ingenier\u00eda de Sistemas y Autom\u00e1tica, Tecnolog\u00eda Electr\u00f3nica y Electr\u00f3nica, Universidad de C\u00e1diz, Escuela Superior de Ingenier\u00eda, C/Chile 1, 11003 C\u00e1diz, Spain","institution_ids":["https://openalex.org/I39147953"]},{"raw_affiliation_string":"Universidad de Sevilla","institution_ids":["https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2808,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.54479544,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"15","issue":"01","first_page":"43","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8404476642608643},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5534998774528503},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5424637794494629},{"id":"https://openalex.org/keywords/transfer","display_name":"Transfer (computing)","score":0.5301144123077393},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.5197803378105164},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.511916995048523},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49390703439712524},{"id":"https://openalex.org/keywords/direct-memory-access","display_name":"Direct memory access","score":0.45415061712265015},{"id":"https://openalex.org/keywords/event","display_name":"Event (particle physics)","score":0.430597186088562},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4187895357608795},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.4135493040084839},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3389182686805725},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.23739701509475708}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8404476642608643},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5534998774528503},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5424637794494629},{"id":"https://openalex.org/C2776175482","wikidata":"https://www.wikidata.org/wiki/Q1195816","display_name":"Transfer (computing)","level":2,"score":0.5301144123077393},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.5197803378105164},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.511916995048523},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49390703439712524},{"id":"https://openalex.org/C37724790","wikidata":"https://www.wikidata.org/wiki/Q210813","display_name":"Direct memory access","level":3,"score":0.45415061712265015},{"id":"https://openalex.org/C2779662365","wikidata":"https://www.wikidata.org/wiki/Q5416694","display_name":"Event (particle physics)","level":2,"score":0.430597186088562},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4187895357608795},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.4135493040084839},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3389182686805725},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.23739701509475708},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1142/s0218126606002927","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126606002927","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},{"id":"pmh:oai:dnet:idus________::42bc23fb584320fbaedbbd78bad464b9","is_oa":false,"landing_page_url":"https://idus.us.es/handle//11441/91264","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1966785807","https://openalex.org/W1971636727","https://openalex.org/W1975617343","https://openalex.org/W1976767905","https://openalex.org/W1996832242","https://openalex.org/W2002554499","https://openalex.org/W2018426736","https://openalex.org/W2023708961","https://openalex.org/W2029115316","https://openalex.org/W2042064944","https://openalex.org/W2049631480","https://openalex.org/W2075927568","https://openalex.org/W2097872138","https://openalex.org/W2107916517","https://openalex.org/W2112833506","https://openalex.org/W2121610900","https://openalex.org/W2140043093","https://openalex.org/W2144101462","https://openalex.org/W2151173903","https://openalex.org/W2159117078","https://openalex.org/W2321832090","https://openalex.org/W2765048691"],"related_works":["https://openalex.org/W2385641813","https://openalex.org/W10042887","https://openalex.org/W2314909823","https://openalex.org/W2222339110","https://openalex.org/W1897440242","https://openalex.org/W1554378476","https://openalex.org/W2218233845","https://openalex.org/W2370550542","https://openalex.org/W2185401572","https://openalex.org/W2387213283"],"abstract_inverted_index":{"Nowadays,":[0],"computers":[1],"are":[2,48],"frequently":[3],"equipped":[4],"with":[5,50],"peripherals":[6,32,74,116],"that":[7,69,100],"transfer":[8],"great":[9],"amounts":[10],"of":[11,43,82,85,127],"data":[12,59],"between":[13],"them":[14],"and":[15,105,139,144],"the":[16,34,66,80,111,115,125],"system":[17,38,51],"memory":[18,21,39,52,107],"using":[19],"direct":[20],"access":[22],"techniques":[23],"(i.e.,":[24,45],"digital":[25],"cameras,":[26],"high":[27,141],"speed":[28,142],"networks,":[29],"\u2026).":[30],"Those":[31],"prevent":[33],"processor":[35,77,104],"from":[36,72],"accessing":[37],"for":[40],"significant":[41],"periods":[42],"time":[44],"while":[46],"they":[47],"communicating":[49],"in":[53,131],"order":[54],"to":[55,89,123],"send":[56],"or":[57],"receive":[58],"blocks).":[60],"In":[61],"this":[62],"paper":[63],"we":[64,94],"study":[65],"negative":[67],"effects":[68],"I/O":[70,112,133],"operations":[71],"computer":[73,103],"have":[75,95],"on":[76],"performance.":[78],"With":[79],"help":[81],"a":[83,97,102],"set":[84],"routines":[86],"(SMPL)":[87],"used":[88,122],"make":[90],"discrete":[91],"event":[92],"simulators,":[93],"developed":[96],"configurable":[98],"software":[99,119],"simulates":[101],"main":[106],"as":[108,110],"well":[109],"scenarios":[113],"where":[114],"operate.":[117],"This":[118],"has":[120],"been":[121],"analyze":[124],"performance":[126],"four":[128,132],"different":[129],"processors":[130],"scenarios:":[134],"video":[135,137],"capture,":[136],"capture":[138],"playback,":[140],"network,":[143],"serial":[145],"transmission.":[146]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
