{"id":"https://openalex.org/W2075668687","doi":"https://doi.org/10.1142/s0218126605002672","title":"INCREMENTAL DESIGN METHODOLOGY FOR MULTIMILLION-GATE FPGAs","display_name":"INCREMENTAL DESIGN METHODOLOGY FOR MULTIMILLION-GATE FPGAs","publication_year":2005,"publication_date":"2005-10-01","ids":{"openalex":"https://openalex.org/W2075668687","doi":"https://doi.org/10.1142/s0218126605002672","mag":"2075668687"},"language":"en","primary_location":{"id":"doi:10.1142/s0218126605002672","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126605002672","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110067569","display_name":"Jing Ma","orcid":null},"institutions":[{"id":"https://openalex.org/I192396691","display_name":"University of New Orleans","ror":"https://ror.org/034mtvk83","country_code":"US","type":"education","lineage":["https://openalex.org/I192396691","https://openalex.org/I2799628689"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"JING MA","raw_affiliation_strings":["Department of Electrical Engineering, University of New Orleans, New Orleans, LA 70148, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of New Orleans, New Orleans, LA 70148, USA","institution_ids":["https://openalex.org/I192396691"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111933984","display_name":"Peter Athanas","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"PETER ATHANAS","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24060, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24060, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042654091","display_name":"Xinming Huang","orcid":"https://orcid.org/0000-0003-0584-3448"},"institutions":[{"id":"https://openalex.org/I192396691","display_name":"University of New Orleans","ror":"https://ror.org/034mtvk83","country_code":"US","type":"education","lineage":["https://openalex.org/I192396691","https://openalex.org/I2799628689"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"XINMING HUANG","raw_affiliation_strings":["Department of Electrical Engineering, University of New Orleans, New Orleans, LA 70148, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of New Orleans, New Orleans, LA 70148, USA","institution_ids":["https://openalex.org/I192396691"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15756854,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":"05","first_page":"1015","last_page":"1026"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8357569575309753},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7065041661262512},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5556709170341492},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.535896897315979},{"id":"https://openalex.org/keywords/design-cycle","display_name":"Design cycle","score":0.47293972969055176},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4596066474914551},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.43661314249038696},{"id":"https://openalex.org/keywords/fidelity","display_name":"Fidelity","score":0.4294899106025696},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3372321128845215},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1416437029838562},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12018999457359314},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.10290953516960144}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8357569575309753},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7065041661262512},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5556709170341492},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.535896897315979},{"id":"https://openalex.org/C2982740150","wikidata":"https://www.wikidata.org/wiki/Q5249230","display_name":"Design cycle","level":2,"score":0.47293972969055176},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4596066474914551},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.43661314249038696},{"id":"https://openalex.org/C2776459999","wikidata":"https://www.wikidata.org/wiki/Q2119376","display_name":"Fidelity","level":2,"score":0.4294899106025696},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3372321128845215},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1416437029838562},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12018999457359314},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.10290953516960144},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1142/s0218126605002672","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218126605002672","pdf_url":null,"source":{"id":"https://openalex.org/S167602672","display_name":"Journal of Circuits Systems and Computers","issn_l":"0218-1266","issn":["0218-1266","1793-6454"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Circuits, Systems and Computers","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.409.7609","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.409.7609","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://ece.wpi.edu/~xhuang/index_files/publications/Ma2005 Incremental Design Methodology for Multimillion-Gate FPGAs (JCSC).pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320314786","display_name":"Xilinx","ror":"https://ror.org/01rb7bk56"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1483017465","https://openalex.org/W1984954427","https://openalex.org/W2019954661","https://openalex.org/W2085374061","https://openalex.org/W2103988312","https://openalex.org/W2168019708","https://openalex.org/W2170702155"],"related_works":["https://openalex.org/W2791836533","https://openalex.org/W3011873630","https://openalex.org/W2904952698","https://openalex.org/W2046320175","https://openalex.org/W2105993342","https://openalex.org/W2107662612","https://openalex.org/W3206828520","https://openalex.org/W2925002129","https://openalex.org/W2066442567","https://openalex.org/W4206631564"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"FPGA":[4,14,91],"design":[5,40,48,92,112],"methodology":[6,113],"that":[7,78,109],"can":[8],"be":[9],"used":[10],"to":[11,23,37],"shorten":[12],"the":[13,19,39,45,53,58,62,71,75,83,99,110,121,126],"design-and-debug":[15],"cycle,":[16],"especially":[17],"as":[18,125],"gate":[20],"counts":[21],"increase":[22],"multimillions.":[24],"Core-based":[25],"incremental":[26,72,100,111],"placement":[27],"algorithms,":[28],"in":[29,115],"conjunction":[30],"with":[31,66],"fast":[32],"interactive":[33],"routing,":[34],"are":[35],"investigated":[36],"reduce":[38],"processing":[41],"time":[42],"by":[43],"distinguishing":[44],"changes":[46],"between":[47],"iterations":[49],"and":[50,102],"reprocessing":[51],"only":[52],"changed":[54],"blocks":[55],"without":[56,130],"affecting":[57],"remaining":[59],"part":[60],"of":[61,117],"design.":[63],"When":[64],"combined":[65],"a":[67],"background":[68,104],"refinement":[69],"thread,":[70],"approach":[73],"offers":[74],"instant":[76],"gratification":[77],"designers":[79],"expect,":[80],"while":[81],"preserving":[82],"fidelity":[84],"attained":[85],"through":[86],"batch-oriented":[87],"programs.":[88],"An":[89],"integrated":[90],"environment":[93],"is":[94,114],"then":[95],"developed":[96],"based":[97],"on":[98],"placer":[101],"its":[103],"refiner.":[105],"The":[106],"results":[107],"show":[108],"orders":[116],"magnitude":[118],"faster":[119],"than":[120],"competing":[122],"approaches":[123],"such":[124],"Xilinx":[127],"M3":[128],"tools":[129],"sacrificing":[131],"too":[132],"much":[133],"quality.":[134]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
