{"id":"https://openalex.org/W2008660517","doi":"https://doi.org/10.1142/s0218001495000213","title":"VLSI IMPLEMENTATION OF AN EFFICIENT ASIC ARCHITECTURE FOR REAL-TIME ROTATION OF DIGITAL IMAGES","display_name":"VLSI IMPLEMENTATION OF AN EFFICIENT ASIC ARCHITECTURE FOR REAL-TIME ROTATION OF DIGITAL IMAGES","publication_year":1995,"publication_date":"1995-04-01","ids":{"openalex":"https://openalex.org/W2008660517","doi":"https://doi.org/10.1142/s0218001495000213","mag":"2008660517"},"language":"en","primary_location":{"id":"doi:10.1142/s0218001495000213","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218001495000213","pdf_url":null,"source":{"id":"https://openalex.org/S41486457","display_name":"International Journal of Pattern Recognition and Artificial Intelligence","issn_l":"0218-0014","issn":["0218-0014","1793-6381"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Pattern Recognition and Artificial Intelligence","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102001964","display_name":"Indradeep Ghosh","orcid":"https://orcid.org/0000-0003-3146-4003"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"INDRADEEP GHOSH","raw_affiliation_strings":["Department of Electrical Engineering Princeton University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering Princeton University, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114252085","display_name":"B. C. Majumdar","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"BANDANA MAJUMDAR","raw_affiliation_strings":["Department of Electronics and Electrical Communication Engineering Indian Institute of Technology, Kharagpur, India","Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, INDIA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Communication Engineering Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]},{"raw_affiliation_string":"Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, INDIA","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.046,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.74884944,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"09","issue":"02","first_page":"449","last_page":"462"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9932000041007996,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9919000267982483,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8661619424819946},{"id":"https://openalex.org/keywords/cordic","display_name":"CORDIC","score":0.70575350522995},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7056453824043274},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7050873041152954},{"id":"https://openalex.org/keywords/frame-rate","display_name":"Frame rate","score":0.6906517744064331},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6351008415222168},{"id":"https://openalex.org/keywords/pixel","display_name":"Pixel","score":0.6120968461036682},{"id":"https://openalex.org/keywords/rotation","display_name":"Rotation (mathematics)","score":0.5959018468856812},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5725115537643433},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.48388728499412537},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.45368775725364685},{"id":"https://openalex.org/keywords/frame","display_name":"Frame (networking)","score":0.4172777533531189},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2889935374259949},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.2780584394931793},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.2500787675380707},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1382155418395996},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09842169284820557}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8661619424819946},{"id":"https://openalex.org/C58870171","wikidata":"https://www.wikidata.org/wiki/Q116076","display_name":"CORDIC","level":3,"score":0.70575350522995},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7056453824043274},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7050873041152954},{"id":"https://openalex.org/C3261483","wikidata":"https://www.wikidata.org/wiki/Q119565","display_name":"Frame rate","level":2,"score":0.6906517744064331},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6351008415222168},{"id":"https://openalex.org/C160633673","wikidata":"https://www.wikidata.org/wiki/Q355198","display_name":"Pixel","level":2,"score":0.6120968461036682},{"id":"https://openalex.org/C74050887","wikidata":"https://www.wikidata.org/wiki/Q848368","display_name":"Rotation (mathematics)","level":2,"score":0.5959018468856812},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5725115537643433},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48388728499412537},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.45368775725364685},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.4172777533531189},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2889935374259949},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2780584394931793},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.2500787675380707},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1382155418395996},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09842169284820557}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0218001495000213","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0218001495000213","pdf_url":null,"source":{"id":"https://openalex.org/S41486457","display_name":"International Journal of Pattern Recognition and Artificial Intelligence","issn_l":"0218-0014","issn":["0218-0014","1793-6381"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Pattern Recognition and Artificial Intelligence","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1609220141","https://openalex.org/W2123696527","https://openalex.org/W2163915119","https://openalex.org/W1572837867","https://openalex.org/W2141748053","https://openalex.org/W1836199784","https://openalex.org/W2053098484","https://openalex.org/W4311412447","https://openalex.org/W2122785682","https://openalex.org/W2575964431"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,6,42,61,86,118,127],"design":[4,68,90],"and":[5,104,140],"VLSI":[7],"implementation":[8],"of":[9,32,36,45,63,102,120,129,146],"a":[10,30,49,64,72,100,108,121],"novel":[11],"architecture":[12],"that":[13,74],"performs":[14],"image":[15,125],"rotation":[16,35,119],"in":[17],"real":[18],"time.":[19],"In":[20],"order":[21],"to":[22,59,99],"improve":[23],"throughput,":[24],"we":[25,115],"divide":[26],"an":[27,142],"image-frame":[28],"into":[29,71],"number":[31],"windows.":[33],"The":[34,92,134],"each":[37],"window-center":[38],"as":[39,41],"well":[40],"final":[43],"displacement":[44,62],"individual":[46],"pixels":[47],"within":[48],"window":[50],"is":[51,57,69],"then":[52],"calculated.":[53],"A":[54],"CORDIC-based":[55],"scheme":[56],"used":[58],"compute":[60],"pixel.":[65],"Our":[66],"architectural":[67],"incorporated":[70],"chip":[73,93,135],"has":[75,141],"been":[76],"laid":[77],"out":[78],"using":[79],"VTI":[80],"(VLSI":[81],"Technology":[82],"Inc.)":[83],"tools":[84],"obeying":[85],"1.5":[87],"\u03bcm":[88],"SCMOS":[89],"rules.":[91],"owes":[94],"its":[95],"high":[96],"processing":[97],"capability":[98],"combination":[101],"pipelining":[103],"parallel-processing":[105],"techniques.":[106],"For":[107],"clock":[109],"frequency":[110],"greater":[111],"than":[112],"10.6":[113],"MHz,":[114],"can":[116],"perform":[117],"512\u00d7512":[122],"gray-level":[123],"digital":[124],"at":[126],"rate":[128],"30":[130],"frames":[131],"per":[132],"second.":[133],"utilizes":[136],"around":[137],"35,000":[138],"transistors":[139],"estimated":[143],"silicon":[144],"area":[145],"211":[147],"mils\u00d7276":[148],"mils.":[149]},"counts_by_year":[],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}