{"id":"https://openalex.org/W1989998971","doi":"https://doi.org/10.1142/s0129626408003387","title":"ADAPTIVE COMMUNICATION ARCHITECTURES FOR RUNTIME RECONFIGURABLE SYSTEM-ON-CHIPS","display_name":"ADAPTIVE COMMUNICATION ARCHITECTURES FOR RUNTIME RECONFIGURABLE SYSTEM-ON-CHIPS","publication_year":2008,"publication_date":"2008-05-29","ids":{"openalex":"https://openalex.org/W1989998971","doi":"https://doi.org/10.1142/s0129626408003387","mag":"1989998971"},"language":"en","primary_location":{"id":"doi:10.1142/s0129626408003387","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129626408003387","pdf_url":null,"source":{"id":"https://openalex.org/S18360026","display_name":"Parallel Processing Letters","issn_l":"0129-6264","issn":["0129-6264","1793-642X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Processing Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080637249","display_name":"Thilo Pionteck","orcid":"https://orcid.org/0000-0001-6518-1226"},"institutions":[{"id":"https://openalex.org/I9341345","display_name":"University of L\u00fcbeck","ror":"https://ror.org/00t3r8h32","country_code":"DE","type":"education","lineage":["https://openalex.org/I9341345"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"THILO PIONTECK","raw_affiliation_strings":["Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany","institution_ids":["https://openalex.org/I9341345"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111901390","display_name":"Carsten Albrecht","orcid":null},"institutions":[{"id":"https://openalex.org/I9341345","display_name":"University of L\u00fcbeck","ror":"https://ror.org/00t3r8h32","country_code":"DE","type":"education","lineage":["https://openalex.org/I9341345"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"CARSTEN ALBRECHT","raw_affiliation_strings":["Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany","institution_ids":["https://openalex.org/I9341345"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113608746","display_name":"Roman Koch","orcid":null},"institutions":[{"id":"https://openalex.org/I9341345","display_name":"University of L\u00fcbeck","ror":"https://ror.org/00t3r8h32","country_code":"DE","type":"education","lineage":["https://openalex.org/I9341345"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"ROMAN KOCH","raw_affiliation_strings":["Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany","institution_ids":["https://openalex.org/I9341345"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047630768","display_name":"Erik Maehle","orcid":null},"institutions":[{"id":"https://openalex.org/I9341345","display_name":"University of L\u00fcbeck","ror":"https://ror.org/00t3r8h32","country_code":"DE","type":"education","lineage":["https://openalex.org/I9341345"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"ERIK MAEHLE","raw_affiliation_strings":["Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering, University of L\u00fcbeck, Ratzeburger Allee 160, 23564 L\u00fcbeck, Germany","institution_ids":["https://openalex.org/I9341345"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I9341345"],"apc_list":null,"apc_paid":null,"fwci":1.907,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.8685347,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"18","issue":"02","first_page":"275","last_page":"289"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9894000291824341,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8077359199523926},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5530433058738708},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5194589495658875},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4985382556915283},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.48802176117897034},{"id":"https://openalex.org/keywords/adaptability","display_name":"Adaptability","score":0.47844862937927246},{"id":"https://openalex.org/keywords/runtime-system","display_name":"Runtime system","score":0.4720799922943115},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.44684097170829773},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4394104480743408},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41061919927597046}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8077359199523926},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5530433058738708},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5194589495658875},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4985382556915283},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.48802176117897034},{"id":"https://openalex.org/C177606310","wikidata":"https://www.wikidata.org/wiki/Q5674297","display_name":"Adaptability","level":2,"score":0.47844862937927246},{"id":"https://openalex.org/C2780870223","wikidata":"https://www.wikidata.org/wiki/Q1004415","display_name":"Runtime system","level":2,"score":0.4720799922943115},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.44684097170829773},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4394104480743408},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41061919927597046},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1142/s0129626408003387","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129626408003387","pdf_url":null,"source":{"id":"https://openalex.org/S18360026","display_name":"Parallel Processing Letters","issn_l":"0129-6264","issn":["0129-6264","1793-642X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Processing Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2103839010","https://openalex.org/W2160642395","https://openalex.org/W2162944278","https://openalex.org/W4253638730"],"related_works":["https://openalex.org/W2357124094","https://openalex.org/W2387399993","https://openalex.org/W2389739210","https://openalex.org/W2348924972","https://openalex.org/W2365736347","https://openalex.org/W2047454415","https://openalex.org/W2070040999","https://openalex.org/W2387293848","https://openalex.org/W3121791438","https://openalex.org/W2250140200"],"abstract_inverted_index":{"For":[0],"exploiting":[1],"the":[2,20,90,100,107,110,124,132,141],"inherent":[3],"parallelism":[4],"enclosed":[5],"in":[6,60,74,81,102],"System-on-Chip":[7,50,77,148],"designs,":[8],"special":[9],"architectural":[10],"prerequisites":[11,17],"have":[12],"to":[13,118,161],"be":[14],"met.":[15],"These":[16],"mainly":[18],"affect":[19],"communication":[21,41,66,69,163],"infrastructure,":[22],"as":[23],"parallel":[24],"processing":[25,58],"of":[26,37,57,92,109,136,143,170,178],"all":[27],"hardware":[28],"modules":[29,59],"accounts":[30],"for":[31,47,72,89,99,149],"a":[32,48,87,94,144,158,167,175],"continuous":[33],"and":[34,55,174],"sufficient":[35],"provision":[36],"data.":[38],"While":[39],"traditional":[40],"architectures":[42,70,164],"may":[43],"fulfill":[44],"these":[45],"requirements":[46],"fixed":[49],"design,":[51],"changing":[52],"composition,":[53],"number":[54],"locations":[56],"runtime":[61,75,95,114,127,146,173],"reconfigurable":[62,76,96,147],"System-on-Chips":[63],"require":[64],"new":[65],"paradigms.":[67],"Special":[68],"especially":[71],"use":[73],"designs":[78],"are":[79],"presented":[80],"this":[82],"article.":[83],"Their":[84],"analysis":[85],"provides":[86],"basis":[88,142],"design":[91],"CoNoChi,":[93],"Network-on-Chip":[97],"dedicated":[98],"usage":[101],"FPGA-based":[103],"designs.":[104],"CoNoChi":[105,137,156],"supports":[106],"adaptation":[108],"network":[111,125],"topology":[112],"during":[113,126,172],"by":[115],"providing":[116],"mechanisms":[117],"add":[119],"or":[120,130],"remove":[121],"switches":[122],"from":[123],"without":[128],"stopping":[129],"stalling":[131],"network.":[133],"The":[134],"applicability":[135],"is":[138,157],"shown":[139],"on":[140],"complex":[145],"networking":[150],"applications.":[151],"Prototyping":[152],"results":[153],"demonstrate":[154],"that":[155],"promising":[159],"alternative":[160],"existing":[162],"supporting":[165],"both":[166],"high":[168,176],"degree":[169],"adaptability":[171],"concurrency":[177],"data":[179],"transfers.":[180]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}