{"id":"https://openalex.org/W2025897912","doi":"https://doi.org/10.1142/s0129626406002587","title":"MICROTHREADING A MODEL FOR DISTRIBUTED INSTRUCTION-LEVEL CONCURRENCY","display_name":"MICROTHREADING A MODEL FOR DISTRIBUTED INSTRUCTION-LEVEL CONCURRENCY","publication_year":2006,"publication_date":"2006-06-01","ids":{"openalex":"https://openalex.org/W2025897912","doi":"https://doi.org/10.1142/s0129626406002587","mag":"2025897912"},"language":"en","primary_location":{"id":"doi:10.1142/s0129626406002587","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129626406002587","pdf_url":null,"source":{"id":"https://openalex.org/S18360026","display_name":"Parallel Processing Letters","issn_l":"0129-6264","issn":["0129-6264","1793-642X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Processing Letters","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077847640","display_name":"Chris Jesshope","orcid":null},"institutions":[{"id":"https://openalex.org/I887064364","display_name":"University of Amsterdam","ror":"https://ror.org/04dkp9463","country_code":"NL","type":"education","lineage":["https://openalex.org/I887064364"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"CHRIS JESSHOPE","raw_affiliation_strings":["Department of Computer Science, University of Amsterdam, Kruislaan 403, Amsterdam, 1098SJ, NL, The Netherlands"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Amsterdam, Kruislaan 403, Amsterdam, 1098SJ, NL, The Netherlands","institution_ids":["https://openalex.org/I887064364"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5077847640"],"corresponding_institution_ids":["https://openalex.org/I887064364"],"apc_list":null,"apc_paid":null,"fwci":1.9655,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.85458312,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"16","issue":"02","first_page":"209","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8816169500350952},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.7832210063934326},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.723324716091156},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6753373146057129},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.6650312542915344},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.444794625043869},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.426474392414093},{"id":"https://openalex.org/keywords/memory-model","display_name":"Memory model","score":0.4195230007171631},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3859094977378845},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34391477704048157},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.32649707794189453},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18964093923568726}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8816169500350952},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.7832210063934326},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.723324716091156},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6753373146057129},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.6650312542915344},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.444794625043869},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.426474392414093},{"id":"https://openalex.org/C12186640","wikidata":"https://www.wikidata.org/wiki/Q6815743","display_name":"Memory model","level":3,"score":0.4195230007171631},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3859094977378845},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34391477704048157},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.32649707794189453},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18964093923568726},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1142/s0129626406002587","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129626406002587","pdf_url":null,"source":{"id":"https://openalex.org/S18360026","display_name":"Parallel Processing Letters","issn_l":"0129-6264","issn":["0129-6264","1793-642X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Parallel Processing Letters","raw_type":"journal-article"},{"id":"pmh:oai:dare.uva.nl:openaire_cris_publications/109c99f8-e279-4455-a66f-da07c17e92da","is_oa":false,"landing_page_url":"https://handle.uba.uva.nl/personal/pure/en/publications/microthreading-a-model-for-distributed-instructionlevel-concurrency(109c99f8-e279-4455-a66f-da07c17e92da).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Jesshope, C R 2006, 'Microthreading, a Model for Distributed Instruction-level Concurrency', Parallel Processing Letters, vol. 16, no. 2, pp. 209-228.","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:dare.uva.nl:publications/109c99f8-e279-4455-a66f-da07c17e92da","is_oa":false,"landing_page_url":"http://dare.uva.nl/personal/pure/en/publications/microthreading-a-model-for-distributed-instructionlevel-concurrency(109c99f8-e279-4455-a66f-da07c17e92da).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400088","display_name":"UvA-DARE (University of Amsterdam)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887064364","host_organization_name":"University of Amsterdam","host_organization_lineage":["https://openalex.org/I887064364"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Jesshope, C R 2006, 'Microthreading, a Model for Distributed Instruction-level Concurrency', Parallel Processing Letters, vol. 16, no. 2, pp. 209-228.","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:uvapub:oai:dare.uva.nl:publications/109c99f8-e279-4455-a66f-da07c17e92da","is_oa":false,"landing_page_url":"https://dare.uva.nl/personal/pure/en/publications/microthreading-a-model-for-distributed-instructionlevel-concurrency(109c99f8-e279-4455-a66f-da07c17e92da).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Parallel Processing Letters, 16(2), 209 - 228. World Scientific Publishing Co. Pte. Ltd.","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1581663820","https://openalex.org/W1983242583","https://openalex.org/W1985410827","https://openalex.org/W2002281184","https://openalex.org/W2006090396","https://openalex.org/W2092931576","https://openalex.org/W2099089002","https://openalex.org/W2110263160","https://openalex.org/W2138030026","https://openalex.org/W2145022480","https://openalex.org/W2146173591","https://openalex.org/W2147345262","https://openalex.org/W2148051985","https://openalex.org/W2150007533","https://openalex.org/W2158094629","https://openalex.org/W2293817904","https://openalex.org/W4252934402"],"related_works":["https://openalex.org/W2169019163","https://openalex.org/W4317827391","https://openalex.org/W40577698","https://openalex.org/W1839004754","https://openalex.org/W2497938157","https://openalex.org/W4233212676","https://openalex.org/W184932080","https://openalex.org/W934691044","https://openalex.org/W4300963581","https://openalex.org/W1597188213"],"abstract_inverted_index":{"This":[0,56],"paper":[1,57],"analyses":[2],"the":[3,59,64,75,85,118,123],"micro-threaded":[4,38],"model":[5,17,39,86,93],"of":[6,67,77,97,103,115],"concurrency":[7],"making":[8,29],"comparisons":[9],"with":[10,79],"both":[11,135],"data":[12],"and":[13,21,73,87,100,128,137],"instruction-level":[14],"concurrency.":[15],"The":[16,37,92,109],"is":[18,134],"fine":[19],"grain":[20],"provides":[22],"synchronisation":[23],"in":[24,43,52,89],"a":[25,31,46],"distributed":[26],"register":[27,119],"file,":[28],"it":[30,133],"promising":[32],"candidate":[33],"for":[34,70],"scalable":[35],"chip-multiprocessors.":[36],"was":[40],"first":[41],"proposed":[42],"1996":[44],"as":[45],"means":[47],"to":[48,62,81,125],"tolerate":[49],"high":[50],"latencies":[51],"data-parallel,":[53],"distributed-memory":[54],"multi-processors.":[55],"explores":[58],"model's":[60],"opportunity":[61],"provide":[63],"simultaneous":[65],"issue":[66],"instructions,":[68],"required":[69],"chip":[71],"multiprocessors,":[72],"discusses":[74],"issues":[76],"scalability":[78],"regard":[80],"support":[82],"structures":[83],"implementing":[84],"communication":[88,130],"supporting":[90],"it.":[91],"supports":[94],"deterministic":[95],"distribution":[96],"code":[98],"fragments":[99],"dynamic":[101],"scheduling":[102],"instructions":[104],"from":[105,117],"within":[106],"those":[107],"fragments.":[108],"hardware":[110,124],"also":[111],"recognises":[112],"different":[113],"classes":[114],"variables":[116],"specifiers,":[120],"which":[121],"allows":[122],"manage":[126],"locality":[127],"optimise":[129],"so":[131],"that":[132],"efficient":[136],"scalable.":[138]},"counts_by_year":[{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}