{"id":"https://openalex.org/W2029041900","doi":"https://doi.org/10.1142/s0129065700000193","title":"SIMULINK-BASED HW/SW CODESIGN OF EMBEDDED NEURO-FUZZY SYSTEMS","display_name":"SIMULINK-BASED HW/SW CODESIGN OF EMBEDDED NEURO-FUZZY SYSTEMS","publication_year":2000,"publication_date":"2000-06-01","ids":{"openalex":"https://openalex.org/W2029041900","doi":"https://doi.org/10.1142/s0129065700000193","mag":"2029041900","pmid":"https://pubmed.ncbi.nlm.nih.gov/11011793"},"language":"en","primary_location":{"id":"doi:10.1142/s0129065700000193","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129065700000193","pdf_url":null,"source":{"id":"https://openalex.org/S197665576","display_name":"International Journal of Neural Systems","issn_l":"0129-0657","issn":["0129-0657","1793-6462"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Neural Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref","pubmed"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036615305","display_name":"Leonardo Reyneri","orcid":"https://orcid.org/0000-0002-4154-3146"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"L. M. Reyneri","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy","Dipartimento di Elettronica, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009477620","display_name":"Marcello Chiaberge","orcid":"https://orcid.org/0000-0002-1921-0126"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Chiaberge","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy","Dipartimento di Elettronica, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050365912","display_name":"Luciano Lavagno","orcid":"https://orcid.org/0000-0002-9762-6522"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Lavagno","raw_affiliation_strings":["Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy","Dipartimento di Elettronica, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031851267","display_name":"B. Pino","orcid":null},"institutions":[{"id":"https://openalex.org/I173304897","display_name":"Universidad de Granada","ror":"https://ror.org/04njjy449","country_code":"ES","type":"education","lineage":["https://openalex.org/I173304897"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"B. Pino","raw_affiliation_strings":["Dep.to de Arquitectura y Tecnologia de Computadores, Univ. de Granada, Campus Universitario de Fuentenueva, Granada, Spain"],"affiliations":[{"raw_affiliation_string":"Dep.to de Arquitectura y Tecnologia de Computadores, Univ. de Granada, Campus Universitario de Fuentenueva, Granada, Spain","institution_ids":["https://openalex.org/I173304897"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071496825","display_name":"Eduardo Reck Miranda","orcid":"https://orcid.org/0000-0002-8306-9585"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"E. Miranda","raw_affiliation_strings":["Mechatronics Lab, Politecnico di Torino, C.so Duca degli Abruzzi,  24, 10129 Torino, Italy","Mechatronics Lab, Politecnico di Torino, C.so Duca degli Abruzzi, 24, 10129 Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Mechatronics Lab, Politecnico di Torino, C.so Duca degli Abruzzi,  24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]},{"raw_affiliation_string":"Mechatronics Lab, Politecnico di Torino, C.so Duca degli Abruzzi, 24, 10129 Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5036615305"],"corresponding_institution_ids":["https://openalex.org/I177477856"],"apc_list":null,"apc_paid":null,"fwci":2.1288,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.87775281,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"10","issue":"03","first_page":"211","last_page":"226"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10820","display_name":"Fuzzy Logic and Control Systems","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8131898641586304},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6845206618309021},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.611240565776825},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5350659489631653},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4860682785511017},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.48277726769447327},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.45933404564857483},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4511135220527649},{"id":"https://openalex.org/keywords/fuzzy-logic","display_name":"Fuzzy logic","score":0.44482994079589844},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.44046151638031006},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.37990665435791016},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10747742652893066},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08017164468765259}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8131898641586304},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6845206618309021},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.611240565776825},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5350659489631653},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4860682785511017},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.48277726769447327},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.45933404564857483},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4511135220527649},{"id":"https://openalex.org/C58166","wikidata":"https://www.wikidata.org/wiki/Q224821","display_name":"Fuzzy logic","level":2,"score":0.44482994079589844},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.44046151638031006},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.37990665435791016},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10747742652893066},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08017164468765259},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[{"descriptor_ui":"D000703","descriptor_name":"Analog-Digital Conversion","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D000703","descriptor_name":"Analog-Digital Conversion","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D000703","descriptor_name":"Analog-Digital Conversion","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D003198","descriptor_name":"Computer Simulation","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D003198","descriptor_name":"Computer Simulation","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D003198","descriptor_name":"Computer Simulation","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D008959","descriptor_name":"Models, Neurological","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D008959","descriptor_name":"Models, Neurological","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D008959","descriptor_name":"Models, Neurological","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D012984","descriptor_name":"Software","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D012984","descriptor_name":"Software","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D012984","descriptor_name":"Software","qualifier_ui":null,"qualifier_name":null,"is_major_topic":false},{"descriptor_ui":"D016571","descriptor_name":"Neural Networks, Computer","qualifier_ui":null,"qualifier_name":null,"is_major_topic":true},{"descriptor_ui":"D016571","descriptor_name":"Neural Networks, Computer","qualifier_ui":null,"qualifier_name":null,"is_major_topic":true},{"descriptor_ui":"D016571","descriptor_name":"Neural Networks, Computer","qualifier_ui":null,"qualifier_name":null,"is_major_topic":true},{"descriptor_ui":"D017143","descriptor_name":"Fuzzy Logic","qualifier_ui":null,"qualifier_name":null,"is_major_topic":true},{"descriptor_ui":"D017143","descriptor_name":"Fuzzy Logic","qualifier_ui":null,"qualifier_name":null,"is_major_topic":true},{"descriptor_ui":"D017143","descriptor_name":"Fuzzy Logic","qualifier_ui":null,"qualifier_name":null,"is_major_topic":true}],"locations_count":3,"locations":[{"id":"doi:10.1142/s0129065700000193","is_oa":false,"landing_page_url":"https://doi.org/10.1142/s0129065700000193","pdf_url":null,"source":{"id":"https://openalex.org/S197665576","display_name":"International Journal of Neural Systems","issn_l":"0129-0657","issn":["0129-0657","1793-6462"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319815","host_organization_name":"World Scientific","host_organization_lineage":["https://openalex.org/P4310319815"],"host_organization_lineage_names":["World Scientific"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Neural Systems","raw_type":"journal-article"},{"id":"pmid:11011793","is_oa":false,"landing_page_url":"https://pubmed.ncbi.nlm.nih.gov/11011793","pdf_url":null,"source":{"id":"https://openalex.org/S4306525036","display_name":"PubMed","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1299303238","host_organization_name":"National Institutes of Health","host_organization_lineage":["https://openalex.org/I1299303238"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International journal of neural systems","raw_type":null},{"id":"pmh:oai:porto.polito.it:1397895","is_oa":false,"landing_page_url":"http://porto.polito.it/1397895/","pdf_url":null,"source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISSN:0129-0657","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.550000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2085952730","https://openalex.org/W2114972314","https://openalex.org/W2169687938","https://openalex.org/W2172029845","https://openalex.org/W2615865818"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W2364622490","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W2042515040","https://openalex.org/W4297665406","https://openalex.org/W2749962643","https://openalex.org/W2101296662","https://openalex.org/W2390807153","https://openalex.org/W2091330445"],"abstract_inverted_index":{"We":[0,49],"propose":[1],"a":[2],"semi-automatic":[3],"HW/SW":[4],"codesign":[5,36],"flow":[6,37,78],"for":[7,56,60],"low-power":[8],"and":[9,28,42,47,59,69,74,84,91,94,102],"low-cost":[10],"Neuro-Fuzzy":[11,32],"embedded":[12,20],"systems.":[13],"Applications":[14],"range":[15],"from":[16],"fast":[17],"prototyping":[18],"of":[19,25,31,62,105],"systems":[21],"to":[22],"high-speed":[23],"simulation":[24],"Simulink":[26,54],"models":[27],"rapid":[29],"design":[30],"devices.":[33],"The":[34,52,76],"proposed":[35,77],"works":[38],"with":[39],"different":[40],"technologies":[41],"architectures":[43],"(namely,":[44],"software,":[45],"digital":[46,90],"analog).":[48],"have":[50],"used":[51],"Mathworks'":[53],"environment":[55],"functional":[57],"specification":[58],"analysis":[61],"performance":[63],"criteria":[64],"such":[65],"as":[66,86,88],"timing":[67],"(latency":[68],"throughput),":[70],"power":[71],"dissipation,":[72],"size":[73],"cost.":[75],"can":[79,96],"exploit":[80],"trade-offs":[81],"between":[82,89],"SW":[83],"HW":[85],"well":[87],"analog":[92],"implementations,":[93],"it":[95],"generate,":[97],"respectively,":[98],"the":[99,106],"C,":[100],"VHDL":[101],"SKILL":[103],"codes":[104],"selected":[107],"architectures.":[108]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}