{"id":"https://openalex.org/W2080581943","doi":"https://doi.org/10.1137/0217036","title":"Some Geometry for General River Routing","display_name":"Some Geometry for General River Routing","publication_year":1988,"publication_date":"1988-06-01","ids":{"openalex":"https://openalex.org/W2080581943","doi":"https://doi.org/10.1137/0217036","mag":"2080581943"},"language":"en","primary_location":{"id":"doi:10.1137/0217036","is_oa":false,"landing_page_url":"https://doi.org/10.1137/0217036","pdf_url":null,"source":{"id":"https://openalex.org/S153560523","display_name":"SIAM Journal on Computing","issn_l":"0097-5397","issn":["0097-5397","1095-7111"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320508","host_organization_name":"Society for Industrial and Applied Mathematics","host_organization_lineage":["https://openalex.org/P4310320508"],"host_organization_lineage_names":["Society for Industrial and Applied Mathematics"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SIAM Journal on Computing","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111540477","display_name":"Alan Siegel","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Alan Siegel","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5013225896","display_name":"Danny Dolev","orcid":"https://orcid.org/0000-0001-8853-0644"},"institutions":[{"id":"https://openalex.org/I57206974","display_name":"New York University","ror":"https://ror.org/0190ak572","country_code":"US","type":"education","lineage":["https://openalex.org/I57206974"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Danny Dolev","raw_affiliation_strings":["New York University"],"affiliations":[{"raw_affiliation_string":"New York University","institution_ids":["https://openalex.org/I57206974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5111540477"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.083,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.86852665,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"17","issue":"3","first_page":"583","last_page":"605"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.7545278072357178},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6634883880615234},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5206215381622314},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5032834410667419},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.42047736048698425},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.41810768842697144},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.41150110960006714},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3945957124233246},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3748132884502411},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.1991519033908844},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.0850951075553894},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07724469900131226}],"concepts":[{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.7545278072357178},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6634883880615234},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5206215381622314},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5032834410667419},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.42047736048698425},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.41810768842697144},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.41150110960006714},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3945957124233246},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3748132884502411},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.1991519033908844},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0850951075553894},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07724469900131226},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1137/0217036","is_oa":false,"landing_page_url":"https://doi.org/10.1137/0217036","pdf_url":null,"source":{"id":"https://openalex.org/S153560523","display_name":"SIAM Journal on Computing","issn_l":"0097-5397","issn":["0097-5397","1095-7111"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320508","host_organization_name":"Society for Industrial and Applied Mathematics","host_organization_lineage":["https://openalex.org/P4310320508"],"host_organization_lineage_names":["Society for Industrial and Applied Mathematics"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SIAM Journal on Computing","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1655990431","https://openalex.org/W1967575124","https://openalex.org/W1989650529","https://openalex.org/W2017153896"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W4254559750","https://openalex.org/W2998315020","https://openalex.org/W3016208414","https://openalex.org/W2050492524","https://openalex.org/W2104790384","https://openalex.org/W4205718258","https://openalex.org/W2059364457"],"abstract_inverted_index":{"Efficient":[0],"solutions":[1,107],"are":[2,67,94],"given":[3],"to":[4,80,127,140],"compute":[5],"the":[6,21,25,29,33,36,42,53,123,136],"optimal":[7],"placement":[8,102,141],"for":[9,143],"a":[10,49,57,72,98],"pair":[11],"of":[12,75,84,100,114,131,145],"VLSI":[13],"modules":[14,27],"interconnected":[15],"by":[16],"river":[17,133],"routing.":[18],"Specifically,":[19],"let":[20],"(perpendicular)":[22],"distance":[23],"between":[24],"two":[26],"be":[28],"separation,":[30],"and":[31,48,104,135],"call":[32],"(transverse)":[34],"displacement":[35],"offset.":[37],"This":[38],"paper":[39],"principally":[40],"considers":[41],"separation":[43,55],"problem:":[44],"Given":[45],"an":[46],"offset":[47],"wiring":[50],"rule,":[51],"find":[52],"minimum":[54],"permitting":[56],"legal":[58],"wiring.":[59],"The":[60,112],"design":[61],"rules":[62],"might":[63],"use":[64],"wires":[65],"which":[66,96],"exclusively":[68],"rectilinear,":[69],"polygonal":[70],"with":[71],"finite":[73],"number":[74],"slopes,":[76],"or":[77],"possibly":[78],"restricted":[79],"some":[81],"other":[82],"class":[83],"shapes":[85],"such":[86],"as":[87],"circular":[88],"arcs":[89],"plus":[90],"linear":[91],"pieces.":[92],"Techniques":[93],"developed":[95],"unify":[97],"variety":[99],"different":[101],"problems,":[103],"give":[105],"efficient":[106],"under":[108],"extremely":[109],"general":[110],"conditions.":[111],"advantage":[113],"these":[115],"generalizations":[116],"is":[117,138],"not":[118],"only":[119],"their":[120],"theoretical":[121],"framework;":[122],"results":[124],"extend":[125],"naturally":[126],"more":[128],"precise":[129],"models":[130],"real":[132],"routing,":[134],"theory":[137],"applicable":[139],"problems":[142],"collections":[144],"modules.":[146]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}