{"id":"https://openalex.org/W2162987996","doi":"https://doi.org/10.1134/s0361768810060058","title":"Register allocation with instruction scheduling for VLIW-architectures","display_name":"Register allocation with instruction scheduling for VLIW-architectures","publication_year":2010,"publication_date":"2010-11-01","ids":{"openalex":"https://openalex.org/W2162987996","doi":"https://doi.org/10.1134/s0361768810060058","mag":"2162987996"},"language":"en","primary_location":{"id":"doi:10.1134/s0361768810060058","is_oa":false,"landing_page_url":"https://doi.org/10.1134/s0361768810060058","pdf_url":null,"source":{"id":"https://openalex.org/S150218641","display_name":"Programming and Computer Software","issn_l":"0361-7688","issn":["0361-7688","1608-3261"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320267","host_organization_name":"Pleiades Publishing","host_organization_lineage":["https://openalex.org/P4310320267","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Pleiades Publishing","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Programming and Computer Software","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061728949","display_name":"Dmitriy Ivanov","orcid":null},"institutions":[{"id":"https://openalex.org/I153845743","display_name":"Moscow Institute of Physics and Technology","ror":"https://ror.org/00v0z9322","country_code":"RU","type":"education","lineage":["https://openalex.org/I153845743"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"D. S. Ivanov","raw_affiliation_strings":["Moscow Institute of Physics and Technology, Institutskii per. 9, Dolgoprudnyi, Moscow oblast, 141700, Russia","Moscow Institute of Physics and Technology, Dolgoprudnyi, Moscow oblast, Russia"],"affiliations":[{"raw_affiliation_string":"Moscow Institute of Physics and Technology, Institutskii per. 9, Dolgoprudnyi, Moscow oblast, 141700, Russia","institution_ids":["https://openalex.org/I153845743"]},{"raw_affiliation_string":"Moscow Institute of Physics and Technology, Dolgoprudnyi, Moscow oblast, Russia","institution_ids":["https://openalex.org/I153845743"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5061728949"],"corresponding_institution_ids":["https://openalex.org/I153845743"],"apc_list":null,"apc_paid":null,"fwci":0.2497,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.6015226,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"36","issue":"6","first_page":"363","last_page":"367"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.9211462736129761},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.8937239646911621},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8579635620117188},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.7097193002700806},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.648711085319519},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6345932483673096},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.4499635398387909},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3920815587043762},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.27349478006362915},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.1660333275794983},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16584652662277222},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.1580568253993988},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.14601290225982666},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.07428273558616638},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.06872206926345825}],"concepts":[{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.9211462736129761},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8937239646911621},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8579635620117188},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.7097193002700806},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.648711085319519},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6345932483673096},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.4499635398387909},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3920815587043762},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.27349478006362915},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.1660333275794983},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16584652662277222},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.1580568253993988},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.14601290225982666},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.07428273558616638},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.06872206926345825},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1134/s0361768810060058","is_oa":false,"landing_page_url":"https://doi.org/10.1134/s0361768810060058","pdf_url":null,"source":{"id":"https://openalex.org/S150218641","display_name":"Programming and Computer Software","issn_l":"0361-7688","issn":["0361-7688","1608-3261"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310320267","host_organization_name":"Pleiades Publishing","host_organization_lineage":["https://openalex.org/P4310320267","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Pleiades Publishing","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Programming and Computer Software","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","score":0.5400000214576721,"display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W163216920","https://openalex.org/W1494930385","https://openalex.org/W1500117749","https://openalex.org/W1555915743","https://openalex.org/W1577524924","https://openalex.org/W1602314073","https://openalex.org/W1971175321","https://openalex.org/W1979984064","https://openalex.org/W1997230820","https://openalex.org/W2024166156","https://openalex.org/W2035424898","https://openalex.org/W2043834751","https://openalex.org/W2063452410","https://openalex.org/W2114067856","https://openalex.org/W2118866757","https://openalex.org/W2137300667","https://openalex.org/W2164363152","https://openalex.org/W3148529197","https://openalex.org/W3149065374","https://openalex.org/W4214484431","https://openalex.org/W4229550968","https://openalex.org/W4232378942","https://openalex.org/W4250204977","https://openalex.org/W4251068092","https://openalex.org/W4252424613"],"related_works":["https://openalex.org/W2103250493","https://openalex.org/W2137995472","https://openalex.org/W2353958330","https://openalex.org/W2049342712","https://openalex.org/W2911679140","https://openalex.org/W2162987996","https://openalex.org/W1981018241","https://openalex.org/W2347447244","https://openalex.org/W2581286023","https://openalex.org/W2054117411"],"abstract_inverted_index":{"Interaction":[0],"between":[1],"the":[2,19,32,51,57,60,79],"phases":[3,71],"of":[4,22,31,36,53,59,81],"register":[5],"allocation":[6],"and":[7,55],"instruction":[8],"scheduling":[9,83],"are":[10],"often":[11],"considered":[12],"in":[13],"publications":[14],"devoted":[15],"to":[16,28,68],"optimizations":[17],"for":[18,34,78,84],"final":[20],"stage":[21],"compilation.":[23],"Typically,":[24],"it":[25],"is":[26],"proposed":[27],"adapt":[29],"one":[30],"phase":[33],"needs":[35],"another":[37],"without":[38],"their":[39,46],"combination":[40],"into":[41],"a":[42],"single":[43],"unit.":[44],"However,":[45],"integration":[47],"can":[48],"essentially":[49],"reduce":[50],"time":[52],"operation":[54],"enhance":[56],"performance":[58],"resulting":[61],"code.":[62],"This":[63],"study":[64],"describes":[65],"an":[66],"attempt":[67],"combine":[69],"these":[70],"as":[72,74],"completely":[73],"possible":[75],"with":[76],"account":[77],"features":[80],"static":[82],"VLIW-architectures.":[85]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
