{"id":"https://openalex.org/W2144384460","doi":"https://doi.org/10.1109/vtest.1994.292338","title":"Retiming sequential circuits to enhance testability","display_name":"Retiming sequential circuits to enhance testability","publication_year":2002,"publication_date":"2002-12-17","ids":{"openalex":"https://openalex.org/W2144384460","doi":"https://doi.org/10.1109/vtest.1994.292338","mag":"2144384460"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.1994.292338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1994.292338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE VLSI Test Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025308099","display_name":"S. Dey","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"S. Dey","raw_affiliation_strings":["C&C Research Laboratories, NEC USA, Inc., Princeton, NJ, USA","C&C Res. Lab., NEC Res. Inst., Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"C&C Research Laboratories, NEC USA, Inc., Princeton, NJ, USA","institution_ids":[]},{"raw_affiliation_string":"C&C Res. Lab., NEC Res. Inst., Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042424184","display_name":"Srimat Chakradhar","orcid":"https://orcid.org/0000-0003-3530-3901"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.T. Chakradhar","raw_affiliation_strings":["C&C Research Laboratories, NEC USA, Inc., Princeton, NJ, USA","C&C Res. Lab., NEC Res. Inst., Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"C&C Research Laboratories, NEC USA, Inc., Princeton, NJ, USA","institution_ids":[]},{"raw_affiliation_string":"C&C Res. Lab., NEC Res. Inst., Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5025308099"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":3.6961,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":{"value":0.9380909,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"28","last_page":"33"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.9833271503448486},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.9090564250946045},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.7105118036270142},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6699890494346619},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5439207553863525},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5027742385864258},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.49554479122161865},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.42264145612716675},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41089364886283875},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4030470550060272},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2811289429664612},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.20980608463287354},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15735134482383728},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12583881616592407}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9833271503448486},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.9090564250946045},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.7105118036270142},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6699890494346619},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5439207553863525},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5027742385864258},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.49554479122161865},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.42264145612716675},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41089364886283875},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4030470550060272},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2811289429664612},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.20980608463287354},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15735134482383728},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12583881616592407},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vtest.1994.292338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1994.292338","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE VLSI Test Symposium","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2053913299","https://openalex.org/W2070496353","https://openalex.org/W2087656024","https://openalex.org/W2102559735","https://openalex.org/W2116254096","https://openalex.org/W2134626087","https://openalex.org/W2135129887","https://openalex.org/W2135931142","https://openalex.org/W2148631003","https://openalex.org/W2152406824","https://openalex.org/W2161273503","https://openalex.org/W4230587734"],"related_works":["https://openalex.org/W2106178922","https://openalex.org/W4250455229","https://openalex.org/W2107525390","https://openalex.org/W4248668797","https://openalex.org/W2111485030","https://openalex.org/W2125651818","https://openalex.org/W2109248381","https://openalex.org/W2168652618","https://openalex.org/W2127247647","https://openalex.org/W2166402441"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,65],"technique":[4,20,61],"to":[5,47,55,85],"enhance":[6],"the":[7,28,56,74,83,87,92,102,105],"testability":[8,19,109],"of":[9,82,89,104],"sequential":[10,32,99],"circuits":[11,40,100],"by":[12],"repositioning":[13],"registers.":[14],"A":[15],"novel":[16],"retiming":[17,60,107],"for":[18,108],"is":[21,62],"proposed":[22,106],"that":[23,41,71],"reduces":[24],"cycle":[25],"lengths":[26],"in":[27,91],"dependency":[29],"graph,":[30],"converts":[31],"redundancies":[33],"into":[34],"combinational":[35],"redundancies,":[36],"and":[37],"yields":[38],"retimed":[39],"usually":[42],"require":[43],"fewer":[44],"scan":[45],"registers":[46,90],"break":[48],"all":[49,77],"cycles":[50],"(except":[51],"self-loops)":[52],"as":[53],"compared":[54],"original":[57],"circuit.":[58],"The":[59],"based":[63],"on":[64,96],"new":[66],"minimum":[67],"cost":[68],"flow":[69],"formulation":[70],"simultaneously":[72],"considers":[73],"interactions":[75],"among":[76],"strongly":[78],"connected":[79],"components":[80],"(SCCs)":[81],"circuit":[84],"minimize":[86],"number":[88],"SCCs.":[93],"Experimental":[94],"results":[95],"several":[97],"large":[98],"demonstrate":[101],"effectiveness":[103],"technique.<":[110],"<ETX":[111],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[112],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[113]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}