{"id":"https://openalex.org/W2126619051","doi":"https://doi.org/10.1109/vtest.1994.292305","title":"An organization of the test bus for analog and mixed-signal systems","display_name":"An organization of the test bus for analog and mixed-signal systems","publication_year":2002,"publication_date":"2002-12-17","ids":{"openalex":"https://openalex.org/W2126619051","doi":"https://doi.org/10.1109/vtest.1994.292305","mag":"2126619051"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.1994.292305","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1994.292305","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE VLSI Test Symposium","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015145805","display_name":"Janusz A. Starzyk","orcid":"https://orcid.org/0000-0003-2678-5515"},"institutions":[{"id":"https://openalex.org/I4210106879","display_name":"Ohio University","ror":"https://ror.org/01jr3y717","country_code":"US","type":"education","lineage":["https://openalex.org/I4210106879"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"J.A. Starzyk","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ohio University, Athens, OH, USA","Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ohio University, Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013574729","display_name":"Z.H. Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106879","display_name":"Ohio University","ror":"https://ror.org/01jr3y717","country_code":"US","type":"education","lineage":["https://openalex.org/I4210106879"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Z.H. Liu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ohio University, Athens, OH, USA","Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ohio University, Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102359164","display_name":"Jingbo Zou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210106879","display_name":"Ohio University","ror":"https://ror.org/01jr3y717","country_code":"US","type":"education","lineage":["https://openalex.org/I4210106879"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Zou","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Ohio University, Athens, OH, USA","Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Ohio University, Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA","institution_ids":["https://openalex.org/I4210106879"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5015145805"],"corresponding_institution_ids":["https://openalex.org/I4210106879"],"apc_list":null,"apc_paid":null,"fwci":0.6165,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.67090122,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"247","last_page":"251"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.781570553779602},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.7355939745903015},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.6957486271858215},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6304014325141907},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.602474570274353},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.583681046962738},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5491700768470764},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.46361619234085083},{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.45179012417793274},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.40053021907806396},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.27719318866729736},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24069687724113464},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.1788460612297058},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.175045907497406},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1636660397052765}],"concepts":[{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.781570553779602},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.7355939745903015},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.6957486271858215},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6304014325141907},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.602474570274353},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.583681046962738},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5491700768470764},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.46361619234085083},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.45179012417793274},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40053021907806396},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.27719318866729736},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24069687724113464},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.1788460612297058},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.175045907497406},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1636660397052765},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/vtest.1994.292305","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1994.292305","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of IEEE VLSI Test Symposium","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.418.4650","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.418.4650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ohio.edu/people/starzykj/network/Research/Papers/Conferences before 1997/An organization of the test bus for analog and mixed-signal  94.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1636608364","https://openalex.org/W1901574727","https://openalex.org/W2171294065"],"related_works":["https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W1925788181","https://openalex.org/W2128579103","https://openalex.org/W2101761450","https://openalex.org/W4247344346","https://openalex.org/W2099425240","https://openalex.org/W2149724644","https://openalex.org/W2109999133"],"abstract_inverted_index":{"System":[0],"level":[1],"solutions":[2],"for":[3],"error":[4],"detection":[5],"in":[6,13,74,103],"analog":[7,20,57],"and":[8,46,50],"mixed-signal":[9],"circuits":[10],"are":[11,22,35,53,86],"presented":[12],"this":[14],"paper.":[15],"Internal":[16],"blocks":[17],"of":[18],"an":[19,56,108],"circuit":[21],"accessed":[23],"using":[24],"a":[25,38,44,75,93],"technique":[26],"similar":[27],"to":[28,55,69,88],"the":[29,47,70,89,95,104],"boundary":[30],"scan":[31],"organization.":[32],"Test":[33],"points":[34],"controlled":[36],"by":[37],"digital":[39],"control":[40],"signal":[41,49,71,90],"scanned":[42],"into":[43],"system,":[45],"test":[48,51,58,76,97],"results":[52],"connected":[54],"bus.":[59],"Analog":[60],"response":[61],"can":[62,99],"be":[63,100],"verified":[64],"either":[65],"on-line":[66],"without":[67],"interruption":[68],"path,":[72],"or":[73,83],"mode.":[77],"No":[78],"new":[79],"elements":[80],"(like":[81],"virtual":[82],"real":[84],"switches)":[85],"added":[87],"path.":[91],"As":[92],"result":[94],"proposed":[96],"bus":[98],"easily":[101],"incorporated":[102],"existing":[105],"designs":[106],"as":[107],"add-on":[109],"feature":[110],"enhancing":[111],"system":[112],"testability.<":[113],"<ETX":[114],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[115],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[116]},"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
