{"id":"https://openalex.org/W2110078480","doi":"https://doi.org/10.1109/vtest.1991.208139","title":"Issues of integrating the IEEE Std 1149.1 into a gate array","display_name":"Issues of integrating the IEEE Std 1149.1 into a gate array","publication_year":2002,"publication_date":"2002-12-09","ids":{"openalex":"https://openalex.org/W2110078480","doi":"https://doi.org/10.1109/vtest.1991.208139","mag":"2110078480"},"language":"en","primary_location":{"id":"doi:10.1109/vtest.1991.208139","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1991.208139","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101743753","display_name":"R. Iracheta-Cortez","orcid":"https://orcid.org/0000-0002-2811-2341"},"institutions":[{"id":"https://openalex.org/I888729015","display_name":"University of Colorado Colorado Springs","ror":"https://ror.org/054spjc55","country_code":"US","type":"education","lineage":["https://openalex.org/I888729015"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"R. Cortez","raw_affiliation_strings":["United Technologies Microelectronics Center, Inc., Colorado Springs, CO, USA","United Technol. Microelectron. Center, Colorado Springs, CO, USA"],"affiliations":[{"raw_affiliation_string":"United Technologies Microelectronics Center, Inc., Colorado Springs, CO, USA","institution_ids":[]},{"raw_affiliation_string":"United Technol. Microelectron. Center, Colorado Springs, CO, USA","institution_ids":["https://openalex.org/I888729015"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048113805","display_name":"R. Dandapani","orcid":null},"institutions":[{"id":"https://openalex.org/I888729015","display_name":"University of Colorado Colorado Springs","ror":"https://ror.org/054spjc55","country_code":"US","type":"education","lineage":["https://openalex.org/I888729015"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Dandapani","raw_affiliation_strings":["United Technologies Microelectronics Center, Inc., Colorado Springs, CO, USA","United Technol. Microelectron. Center, Colorado Springs, CO, USA"],"affiliations":[{"raw_affiliation_string":"United Technologies Microelectronics Center, Inc., Colorado Springs, CO, USA","institution_ids":[]},{"raw_affiliation_string":"United Technol. Microelectron. Center, Colorado Springs, CO, USA","institution_ids":["https://openalex.org/I888729015"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026796276","display_name":"Mark Yeager","orcid":null},"institutions":[{"id":"https://openalex.org/I888729015","display_name":"University of Colorado Colorado Springs","ror":"https://ror.org/054spjc55","country_code":"US","type":"education","lineage":["https://openalex.org/I888729015"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Yeager","raw_affiliation_strings":["United Technologies Microelectronics Center, Inc., Colorado Springs, CO, USA","United Technol. Microelectron. Center, Colorado Springs, CO, USA"],"affiliations":[{"raw_affiliation_string":"United Technologies Microelectronics Center, Inc., Colorado Springs, CO, USA","institution_ids":[]},{"raw_affiliation_string":"United Technol. Microelectron. Center, Colorado Springs, CO, USA","institution_ids":["https://openalex.org/I888729015"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101743753"],"corresponding_institution_ids":["https://openalex.org/I888729015"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14342474,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"92","last_page":"97"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.8262559771537781},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"Boundary scan","score":0.7763511538505554},{"id":"https://openalex.org/keywords/microelectronics","display_name":"Microelectronics","score":0.7100611925125122},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5505448579788208},{"id":"https://openalex.org/keywords/boundary","display_name":"Boundary (topology)","score":0.5137806534767151},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.46788495779037476},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.44090861082077026},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4377669394016266},{"id":"https://openalex.org/keywords/surface-mount-technology","display_name":"Surface-mount technology","score":0.4263952970504761},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.40429383516311646},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37978804111480713},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3778047263622284},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31141048669815063},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.21234428882598877},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.12433981895446777},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08603158593177795}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.8262559771537781},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.7763511538505554},{"id":"https://openalex.org/C187937830","wikidata":"https://www.wikidata.org/wiki/Q175403","display_name":"Microelectronics","level":2,"score":0.7100611925125122},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5505448579788208},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.5137806534767151},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46788495779037476},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.44090861082077026},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4377669394016266},{"id":"https://openalex.org/C2776584680","wikidata":"https://www.wikidata.org/wiki/Q191042","display_name":"Surface-mount technology","level":3,"score":0.4263952970504761},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.40429383516311646},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37978804111480713},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3778047263622284},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31141048669815063},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.21234428882598877},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.12433981895446777},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08603158593177795},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vtest.1991.208139","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vtest.1991.208139","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1981400123","https://openalex.org/W2166004767","https://openalex.org/W1991035950","https://openalex.org/W2016245341","https://openalex.org/W3149206619","https://openalex.org/W2150046587","https://openalex.org/W2134860735","https://openalex.org/W4391267927","https://openalex.org/W1888803177","https://openalex.org/W2110078480"],"abstract_inverted_index":{"Use":[0],"of":[1,22,37],"boundary-scan":[2],"to":[3,19,34],"test":[4],"systems":[5],"at":[6],"the":[7,20,35,45,62,68],"production":[8],"and":[9,57],"field":[10],"levels":[11],"has":[12],"taken":[13],"on":[14],"a":[15,31],"greater":[16],"importance":[17],"due":[18],"development":[21],"surface":[23],"mount":[24],"technology.":[25],"The":[26],"IEEE":[27],"Standard":[28],"1149.1":[29],"offers":[30],"documented":[32],"approach":[33],"implementation":[36,56],"boundary-scan.":[38],"United":[39],"Technologies":[40],"Microelectronics":[41],"Center":[42],"(UTMC)":[43],"integrated":[44],"standard":[46],"into":[47],"an":[48],"ASIC":[49],"gate":[50],"array;":[51],"this":[52],"paper":[53],"presents":[54],"that":[55],"addresses":[58],"issues":[59],"arising":[60],"from":[61],"integration":[63],"not":[64],"covered":[65],"specifically":[66],"in":[67],"standard.<":[69],"<ETX":[70],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[71],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[72]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
