{"id":"https://openalex.org/W2146999254","doi":"https://doi.org/10.1109/vlsic.2014.6858415","title":"2&lt;sup&gt;nd&lt;/sup&gt; generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology","display_name":"2&lt;sup&gt;nd&lt;/sup&gt; generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W2146999254","doi":"https://doi.org/10.1109/vlsic.2014.6858415","mag":"2146999254"},"language":"en","primary_location":{"id":"doi:10.1109/vlsic.2014.6858415","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2014.6858415","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027957128","display_name":"Mesut Meterelliyoz","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mesut Meterelliyoz","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014054556","display_name":"F. Al-Amoody","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fuad H. Al-amoody","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101505370","display_name":"\u00dcm\u00fct Arslan","orcid":"https://orcid.org/0000-0002-0884-8079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Umut Arslan","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063387912","display_name":"Fatih Hamzaoglu","orcid":"https://orcid.org/0000-0003-3500-5007"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fatih Hamzaoglu","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084805045","display_name":"Luke Hood","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luke Hood","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077427894","display_name":"Manoj B. Lal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Manoj Lal","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103483122","display_name":"Jeffrey L. Miller","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeffrey L. Miller","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004297371","display_name":"Anand Ramasundar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anand Ramasundar","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040670610","display_name":"Dan Soltman","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Soltman","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015065370","display_name":"Ifar Wan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ifar Wan","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066037916","display_name":"Yuxiao Wang","orcid":"https://orcid.org/0009-0004-9454-5972"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yih Wang","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100629178","display_name":"Guomin Zhang","orcid":"https://orcid.org/0000-0002-3503-7431"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Zhang","raw_affiliation_strings":["Intel Corp, Santa Clara, CA, US","Intel..Corporation.. (Santa..Clara.., CA, US)"],"affiliations":[{"raw_affiliation_string":"Intel Corp, Santa Clara, CA, US","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel..Corporation.. (Santa..Clara.., CA, US)","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":12,"corresponding_author_ids":["https://openalex.org/A5027957128"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.61571326,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8634008169174194},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6519030332565308},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.47497862577438354},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43913280963897705},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4243229925632477},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.409831702709198},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3918692469596863},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.28120702505111694},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25560417771339417},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2466963529586792}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8634008169174194},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6519030332565308},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.47497862577438354},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43913280963897705},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4243229925632477},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.409831702709198},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3918692469596863},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28120702505111694},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25560417771339417},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2466963529586792}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsic.2014.6858415","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2014.6858415","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 Symposium on VLSI Circuits Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2034349229","https://openalex.org/W4366783034","https://openalex.org/W1972415042","https://openalex.org/W4313221225","https://openalex.org/W2150642609","https://openalex.org/W2005410346","https://openalex.org/W2044867305","https://openalex.org/W3161676474","https://openalex.org/W2170979950","https://openalex.org/W1900707063"],"abstract_inverted_index":{"2":[0],"<sup":[1],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[2],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">nd</sup>":[3],"generation":[4,19],"1Gbit":[5],"2GHz":[6],"Embedded":[7],"DRAM":[8],"(eDRAM)":[9],"with":[10],"4X":[11,61],"lower":[12],"self":[13],"refresh":[14,69,72],"power":[15,51,57,73],"compared":[16],"to":[17,48],"prior":[18],"is":[20,43,58],"developed":[21],"in":[22,45],"22nm":[23],"Tri-Gate":[24],"CMOS":[25],"technology.":[26],"Retention":[27],"time":[28],"has":[29],"been":[30],"improved":[31],"by":[32,35,60,62],"3X":[33],"(300us@95\u00b0C)":[34],"process":[36],"and":[37],"design":[38,47],"optimizations.":[39],"Source":[40],"synchronous":[41],"clocking":[42],"integrated":[44],"the":[46],"reduce":[49],"clock":[50],"without":[52],"penalizing":[53],"bandwidth.":[54],"Charge":[55],"pump":[56],"reduced":[59],"employing":[63],"comparator":[64],"based":[65],"regulation.":[66],"Temperature":[67],"controlled":[68],"enables":[70],"minimum":[71],"at":[74],"all":[75],"temperature":[76],"conditions.":[77]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}