{"id":"https://openalex.org/W4308575805","doi":"https://doi.org/10.1109/vlsi-soc54400.2022.9939583","title":"ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches","display_name":"ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches","publication_year":2022,"publication_date":"2022-10-03","ids":{"openalex":"https://openalex.org/W4308575805","doi":"https://doi.org/10.1109/vlsi-soc54400.2022.9939583"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc54400.2022.9939583","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc54400.2022.9939583","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100691061","display_name":"Yogesh Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Yogesh Kumar","raw_affiliation_strings":["Indian Institute of Technology,MARS Lab,Department of Computer Science and Engineering,Guwahati,India","Department of Computer Science and Engineering, MARS Lab, Indian Institute of Technology, Guwahati, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,MARS Lab,Department of Computer Science and Engineering,Guwahati,India","institution_ids":["https://openalex.org/I1317621060"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, MARS Lab, Indian Institute of Technology, Guwahati, India","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100647342","display_name":"S. Sivakumar","orcid":"https://orcid.org/0009-0001-3343-4062"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Sivakumar","raw_affiliation_strings":["Indian Institute of Technology,MARS Lab,Department of Computer Science and Engineering,Guwahati,India","Department of Computer Science and Engineering, MARS Lab, Indian Institute of Technology, Guwahati, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,MARS Lab,Department of Computer Science and Engineering,Guwahati,India","institution_ids":["https://openalex.org/I1317621060"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, MARS Lab, Indian Institute of Technology, Guwahati, India","institution_ids":["https://openalex.org/I1317621060"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021641760","display_name":"John Jose","orcid":"https://orcid.org/0000-0002-0314-8778"},"institutions":[{"id":"https://openalex.org/I1317621060","display_name":"Indian Institute of Technology Guwahati","ror":"https://ror.org/0022nd079","country_code":"IN","type":"education","lineage":["https://openalex.org/I1317621060"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"John Jose","raw_affiliation_strings":["Indian Institute of Technology,MARS Lab,Department of Computer Science and Engineering,Guwahati,India","Department of Computer Science and Engineering, MARS Lab, Indian Institute of Technology, Guwahati, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology,MARS Lab,Department of Computer Science and Engineering,Guwahati,India","institution_ids":["https://openalex.org/I1317621060"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, MARS Lab, Indian Institute of Technology, Guwahati, India","institution_ids":["https://openalex.org/I1317621060"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100691061"],"corresponding_institution_ids":["https://openalex.org/I1317621060"],"apc_list":null,"apc_paid":null,"fwci":0.183,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.48391211,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11315","display_name":"Phase-change materials and chalcogenides","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2505","display_name":"Materials Chemistry"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7904301881790161},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.735564112663269},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7310131788253784},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.6194892525672913},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5671960115432739},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.5593981742858887},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.5496051907539368},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.524642288684845},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49422362446784973},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.4764416813850403},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.46927180886268616},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4660566747188568},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.46094876527786255},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.4544622302055359},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.43424832820892334},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4173150956630707},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.2648395299911499},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.2272574007511139}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7904301881790161},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.735564112663269},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7310131788253784},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.6194892525672913},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5671960115432739},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.5593981742858887},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.5496051907539368},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.524642288684845},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49422362446784973},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.4764416813850403},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.46927180886268616},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4660566747188568},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.46094876527786255},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.4544622302055359},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.43424832820892334},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4173150956630707},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.2648395299911499},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.2272574007511139},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc54400.2022.9939583","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc54400.2022.9939583","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1963958751","https://openalex.org/W2012025286","https://openalex.org/W2033811947","https://openalex.org/W2036853599","https://openalex.org/W2055782529","https://openalex.org/W2125428294","https://openalex.org/W2147657366","https://openalex.org/W2258963578","https://openalex.org/W2293828382","https://openalex.org/W2526202524","https://openalex.org/W2548789460","https://openalex.org/W2794941775","https://openalex.org/W3026838713","https://openalex.org/W3036129477","https://openalex.org/W3177352122","https://openalex.org/W4241765545"],"related_works":["https://openalex.org/W2900372418","https://openalex.org/W4285257158","https://openalex.org/W1030357071","https://openalex.org/W1494152240","https://openalex.org/W2171888576","https://openalex.org/W1977963439","https://openalex.org/W2999811406","https://openalex.org/W1589619473","https://openalex.org/W1971441083","https://openalex.org/W4238754064"],"abstract_inverted_index":{"With":[0],"high":[1],"packing":[2],"density":[3],"and":[4,27,77,84,119,130,138,144,150],"low":[5],"leakage":[6],"power,":[7],"Spin":[8],"Transfer":[9],"Torque":[10],"Random":[11],"Access":[12],"Memories":[13],"(STT-RAM)":[14],"are":[15,91,103],"a":[16,60,112,141],"promising":[17],"alternative":[18],"to":[19,32,81],"replace":[20],"traditional":[21],"memory":[22,35,62],"technologies":[23],"such":[24],"as":[25],"SRAM":[26],"DRAM.":[28],"Applications":[29],"will":[30],"continue":[31],"demand":[33],"more":[34,57],"for":[36,106],"processing":[37],"in":[38,59],"the":[39,94,117,126],"coming":[40],"decades.":[41],"To":[42],"achieve":[43],"higher":[44],"cell":[45,63],"density,":[46],"Multi-Level":[47],"Cell":[48,69],"STT-RAM":[49,70,133],"(MLC":[50],"STT-RAM)":[51],"that":[52,114],"can":[53],"store":[54],"two":[55],"or":[56],"bits":[58],"single":[61],"is":[64],"preferred":[65],"over":[66],"Single":[67],"Level":[68],"(SLC":[71],"STT-RAM).":[72],"But":[73],"their":[74],"multistep":[75,88],"read":[76,83],"write":[78,85,89,146],"operations":[79,90],"lead":[80],"significant":[82],"latency.":[86],"The":[87],"also":[92],"affecting":[93],"durability":[95],"of":[96,121,128],"MLC":[97,107,122,132],"STT-RAM.":[98,108],"Specialised":[99],"wear":[100],"levelling":[101],"techniques":[102],"not":[104],"available":[105],"We":[109],"propose":[110],"ENDURA,":[111],"technique":[113],"could":[115],"improve":[116],"lifetime":[118,127],"latency":[120,147],"STT-RAMs.":[123],"ENDURA":[124],"extends":[125],"2MB":[129],"4MB":[131],"L2":[134],"caches":[135],"by":[136,148],"2.05x":[137],"2.59x":[139],"on":[140],"single-core":[142],"system":[143],"reduces":[145],"9.6%":[149],"8.06%":[151],"respectively":[152],"with":[153],"minimal":[154],"overhead.":[155]},"counts_by_year":[{"year":2024,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}