{"id":"https://openalex.org/W2994040587","doi":"https://doi.org/10.1109/vlsi-soc.2019.8920374","title":"SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures","display_name":"SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures","publication_year":2019,"publication_date":"2019-10-01","ids":{"openalex":"https://openalex.org/W2994040587","doi":"https://doi.org/10.1109/vlsi-soc.2019.8920374","mag":"2994040587"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2019.8920374","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2019.8920374","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075519352","display_name":"Chen-Ying Hsieh","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chenying Hsieh","raw_affiliation_strings":["Department of Computer Science, University of California, Irvine, Irvine, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of California, Irvine, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003045043","display_name":"Ardalan Amiri Sani","orcid":"https://orcid.org/0000-0003-0130-587X"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ardalan Amiri Sani","raw_affiliation_strings":["Department of Computer Science, University of California, Irvine, Irvine, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of California, Irvine, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007817952","display_name":"Nikil Dutt","orcid":"https://orcid.org/0000-0002-3060-8119"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nikil Dutt","raw_affiliation_strings":["Department of Computer Science, University of California, Irvine, Irvine, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of California, Irvine, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5075519352"],"corresponding_institution_ids":["https://openalex.org/I204250578"],"apc_list":null,"apc_paid":null,"fwci":1.2038,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.78698148,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6919839382171631},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.689370334148407},{"id":"https://openalex.org/keywords/electronics","display_name":"Electronics","score":0.557647705078125},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5392296314239502},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5336723327636719},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4501596689224243},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4494858682155609},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.42693889141082764},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41016849875450134},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.30075502395629883},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2544357180595398},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.20646512508392334},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19717875123023987}],"concepts":[{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6919839382171631},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.689370334148407},{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.557647705078125},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5392296314239502},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5336723327636719},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4501596689224243},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4494858682155609},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.42693889141082764},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41016849875450134},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.30075502395629883},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2544357180595398},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.20646512508392334},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19717875123023987},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2019.8920374","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2019.8920374","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1552624537","https://openalex.org/W2060884995","https://openalex.org/W2088554613","https://openalex.org/W2121893797","https://openalex.org/W2128120785","https://openalex.org/W2149294210","https://openalex.org/W2155893237","https://openalex.org/W2159911284","https://openalex.org/W2317748259","https://openalex.org/W2525851376","https://openalex.org/W2527815437","https://openalex.org/W2602039909","https://openalex.org/W2920508728","https://openalex.org/W2946303161","https://openalex.org/W6735719987"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030","https://openalex.org/W2041787842","https://openalex.org/W2170504327"],"abstract_inverted_index":{"The":[0],"following":[1],"topics":[2],"are":[3],"dealt":[4],"with:":[5],"multiprocessing":[6],"systems;":[7],"microprocessor":[8],"chips;":[9],"logic":[10,27],"design;":[11,21],"power":[12],"aware":[13],"computing;":[14],"field":[15],"programmable":[16],"gate":[17],"arrays;":[18],"integrated":[19,24],"circuit":[20,25],"low-power":[22],"electronics;":[23],"reliability;":[26],"gates;":[28],"radiation":[29],"hardening":[30],"(electronics).":[31]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}