{"id":"https://openalex.org/W2918328766","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644864","title":"An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations","display_name":"An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2918328766","doi":"https://doi.org/10.1109/vlsi-soc.2018.8644864","mag":"2918328766"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-soc.2018.8644864","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644864","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027840377","display_name":"Zahira Perez-Rivera","orcid":"https://orcid.org/0000-0002-3053-3006"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":true,"raw_author_name":"Zahira Perez","raw_affiliation_strings":["Dept. Electronics, INAOE, Puebla, Mexico"],"affiliations":[{"raw_affiliation_string":"Dept. Electronics, INAOE, Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006378839","display_name":"Hector Villacorta","orcid":"https://orcid.org/0000-0003-4405-4935"},"institutions":[{"id":"https://openalex.org/I4210161008","display_name":"Universidad Polit\u00e9cnica de Aguascalientes","ror":"https://ror.org/05xg5y175","country_code":"MX","type":"education","lineage":["https://openalex.org/I4210161008"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Hector Villacorta","raw_affiliation_strings":["Dept.Posgraduate and Research, Polytechnic University of Aguascalientes, Aguascalientes, Mexico"],"affiliations":[{"raw_affiliation_string":"Dept.Posgraduate and Research, Polytechnic University of Aguascalientes, Aguascalientes, Mexico","institution_ids":["https://openalex.org/I4210161008"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5038219219","display_name":"Victor Champac","orcid":"https://orcid.org/0000-0002-4440-3800"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Victor Champac","raw_affiliation_strings":["Dept. Electronics, INAOE, Puebla, Mexico"],"affiliations":[{"raw_affiliation_string":"Dept. Electronics, INAOE, Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5027840377"],"corresponding_institution_ids":["https://openalex.org/I39824353"],"apc_list":null,"apc_paid":null,"fwci":0.2575,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.59918075,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"77","last_page":"82"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.8082913160324097},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7788246273994446},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.6472780108451843},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5364089608192444},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5139827132225037},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4909711182117462},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47714969515800476},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47389736771583557},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4391981065273285},{"id":"https://openalex.org/keywords/performance-metric","display_name":"Performance metric","score":0.41511833667755127},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28728997707366943},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24757665395736694},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1271359920501709}],"concepts":[{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.8082913160324097},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7788246273994446},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.6472780108451843},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5364089608192444},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5139827132225037},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4909711182117462},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47714969515800476},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47389736771583557},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4391981065273285},{"id":"https://openalex.org/C2780898871","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Performance metric","level":2,"score":0.41511833667755127},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28728997707366943},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24757665395736694},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1271359920501709},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C187736073","wikidata":"https://www.wikidata.org/wiki/Q2920921","display_name":"Management","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-soc.2018.8644864","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-soc.2018.8644864","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1934058775","https://openalex.org/W1966741973","https://openalex.org/W1967709031","https://openalex.org/W2006589289","https://openalex.org/W2018058223","https://openalex.org/W2100661413","https://openalex.org/W2115674461","https://openalex.org/W2132438916","https://openalex.org/W2157210245","https://openalex.org/W2167077570","https://openalex.org/W2171736840","https://openalex.org/W2418937170","https://openalex.org/W2613115383"],"related_works":["https://openalex.org/W4361804730","https://openalex.org/W2142113611","https://openalex.org/W2334467465","https://openalex.org/W2018387840","https://openalex.org/W2087870008","https://openalex.org/W2045629210","https://openalex.org/W2162534555","https://openalex.org/W2752178021","https://openalex.org/W2143024819","https://openalex.org/W4247159817"],"abstract_inverted_index":{"Due":[0],"to":[1,64,87,106,110],"aggressive":[2],"technology":[3],"scaling":[4],"in":[5,44,72],"nanometer":[6],"regime,":[7],"the":[8,45,52,66,73,83],"impact":[9],"of":[10,34,54,68,75],"process":[11,78],"variations":[12,21],"on":[13,38],"IC":[14],"design":[15],"has":[16],"become":[17],"a":[18,95,104],"challenge.":[19],"Process":[20],"are":[22,48],"usually":[23],"classified":[24],"into":[25],"two":[26],"types:":[27],"inter-die":[28],"and":[29,47],"intra-die":[30,39,77],"variations.":[31,79],"The":[32,80,99],"focus":[33],"this":[35],"paper":[36],"is":[37,62],"variations,":[40],"which":[41],"were":[42],"ignored":[43],"past,":[46],"now":[49],"significantly":[50],"impacting":[51],"performance":[53,67,93],"modern":[55],"circuits.":[56],"A":[57],"novel":[58],"statistical":[59],"gate-sizing":[60,101],"metric":[61,81,102],"proposed":[63,100],"enhance":[65],"digital":[69],"integrated":[70],"circuits":[71],"presence":[74],"local":[76],"selects":[82],"most":[84],"beneficial":[85],"gates":[86],"be":[88],"resized":[89],"for":[90],"improving":[91],"circuit":[92],"at":[94],"lower":[96],"area":[97],"cost.":[98],"provides":[103],"means":[105],"increase":[107],"yield":[108],"leading":[109],"better":[111],"chip":[112],"revenue.":[113]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}