{"id":"https://openalex.org/W2621578704","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939659","title":"An analytical placer for heterogeneous FPGAs via rough-placed packing","display_name":"An analytical placer for heterogeneous FPGAs via rough-placed packing","publication_year":2017,"publication_date":"2017-04-01","ids":{"openalex":"https://openalex.org/W2621578704","doi":"https://doi.org/10.1109/vlsi-dat.2017.7939659","mag":"2621578704"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2017.7939659","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939659","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040007550","display_name":"Wan-Ning Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Wan-Ning Wu","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104083439","display_name":"Chen Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen Chen","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075275148","display_name":"Ching-Yu Chin","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Yu Chin","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062892490","display_name":"Chun-Kai Wang","orcid":"https://orcid.org/0000-0003-2004-2657"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chun-Kai Wang","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021615416","display_name":"Hung-Ming Chen","orcid":"https://orcid.org/0000-0001-8173-3131"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Ming Chen","raw_affiliation_strings":["Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5040007550"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.1433,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48995001,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7196074724197388},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7070030570030212},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.6148520708084106},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5885829329490662},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.47296327352523804},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.414310485124588},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3704531490802765},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.33991366624832153},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2571938633918762},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22829613089561462},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.1456621289253235},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09472504258155823}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7196074724197388},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7070030570030212},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.6148520708084106},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5885829329490662},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.47296327352523804},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.414310485124588},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3704531490802765},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.33991366624832153},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2571938633918762},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22829613089561462},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1456621289253235},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09472504258155823}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2017.7939659","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2017.7939659","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.699999988079071,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1967661769","https://openalex.org/W1968193130","https://openalex.org/W1986026297","https://openalex.org/W2002641171","https://openalex.org/W2029031086","https://openalex.org/W2075137913","https://openalex.org/W2090317622","https://openalex.org/W2111756578","https://openalex.org/W2114136290","https://openalex.org/W2120129706","https://openalex.org/W2124537194","https://openalex.org/W2137454730","https://openalex.org/W2139637699","https://openalex.org/W2151614223","https://openalex.org/W2154014710","https://openalex.org/W2155316178","https://openalex.org/W4234143391","https://openalex.org/W4249211602","https://openalex.org/W6676886990"],"related_works":["https://openalex.org/W2132668926","https://openalex.org/W2547355295","https://openalex.org/W2042759115","https://openalex.org/W2159053194","https://openalex.org/W1964677779","https://openalex.org/W4318224776","https://openalex.org/W2155675690","https://openalex.org/W2099105040","https://openalex.org/W2169510384","https://openalex.org/W1563562883"],"abstract_inverted_index":{"Packing":[0],"and":[1,22,128,148,150,160],"placement":[2,53,60,80,110,139,147,175],"are":[3,41],"two":[4],"crucial":[5],"stages":[6],"for":[7,62,81,140],"FPGA":[8],"realization.":[9],"In":[10,70,108],"the":[11,14,37,44,52,71,82,87,91,102,109,119,123,137,142,145,158,162,168,174],"design":[12],"flow,":[13],"basic":[15,38,83],"logic":[16,31,39,84],"units,":[17],"such":[18],"as":[19],"look-up-tables":[20],"(LUTs)":[21],"flip-flops":[23],"(FFs),":[24],"have":[25],"to":[26,156],"be":[27],"merged":[28],"into":[29,106],"configurable":[30],"blocks":[32,40,159],"(CLBs)":[33],"before":[34],"placement.":[35],"How":[36],"clustered":[42],"in":[43],"packing":[45,68,72],"stage":[46],"has":[47],"a":[48,66,77,112,151],"great":[49],"impact":[50],"on":[51],"quality.":[54],"This":[55],"work":[56],"presents":[57],"an":[58,96],"analytical":[59],"framework":[61],"heterogeneous":[63],"FPGAs":[64],"through":[65],"rough-placed":[67],"algorithm.":[69],"stage,":[73,111],"we":[74,94],"first":[75],"perform":[76],"fast":[78],"wirelength-driven":[79],"units.":[85],"With":[86],"physical":[88],"information":[89],"from":[90],"initial":[92],"placement,":[93],"implement":[95],"affinity-based":[97],"clustering":[98],"algorithm":[99],"while":[100],"taking":[101],"control":[103],"signal":[104],"constraints":[105],"consideration.":[107],"quadratic":[113],"global":[114,138,146],"placer":[115,133,153],"is":[116,134,154],"implemented":[117],"with":[118],"techniques":[120],"of":[121],"handling":[122],"heterogeneity,":[124],"routing":[125],"congestion":[126],"estimation":[127],"cell":[129],"inflation.":[130],"An":[131],"incremental":[132],"performed":[135],"after":[136],"closing":[141],"gap":[143],"between":[144],"legalization,":[149],"detailed":[152],"adopted":[155],"legalize":[157],"reduce":[161],"wirelength.":[163],"Experimental":[164],"results":[165],"show":[166],"that":[167],"proposed":[169],"methodologies":[170],"can":[171],"effectively":[172],"improve":[173],"solutions.":[176]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
